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A super junction ldmos device

A device and conductivity type technology, applied in the field of high-voltage lateral superjunction semiconductor devices, can solve the problems of difficulty in reducing chip area, large system power consumption, and increasing difficulty in circuit design.

Active Publication Date: 2019-09-27
杭州朋声科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] Although this structure solves the problem of high-voltage level bootstrapping and large system power consumption in the traditional structure, it is difficult to reduce the chip area due to the introduction of multiple FPMOSs that use hole conduction and their current capability is very small.
And the area mismatch between the high-side FPMOS and the low-side nLDMOS will also make the output impedance of the high-side and low-side devices mismatch
Due to the small current capability of FPMOS, this also limits the application of this structure at higher voltage levels
The document "Investigation of a Dual Channel N / P-LDMOS and Application to LDO Linear Voltage Regulation" published by M.Denison et al. A kind of SJ-LDMOS that uses P-column and N-column to conduct electricity at the same time, but the SJ-LDMOS needs two independent gate signals to control the P-channel and N-channel, and the voltage between the two control signals is zero to the operating voltage floating, which requires additional circuit blocks to achieve control
This will greatly increase the difficulty of circuit design and reduce system reliability, and also cause the device to be only suitable for low-voltage applications such as LDO

Method used

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Experimental program
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Embodiment 1

[0031] Figure 4 It shows the cell structure of an SJ-pLDMOS device manufactured on a bulk silicon substrate in the present invention, including: a P-type substrate 1, an N-type source substrate region 2 located on the top layer side of the P-type substrate 1 , the P-type drain region 10 located on the other side of the top layer of the P-type substrate 1, the super junction surface withstand voltage region 15 located on the surface of the substrate 1 between the N-type source substrate region 2 and the P-type drain region 10 , wherein: the material of the P-type substrate 1 can also be an N-type semiconductor material, not limited to the P-type semiconductor disclosed in this embodiment, and the superjunction surface withstand voltage regions 15 have alternately arranged parallel to the lateral direction of the device. The P-type semiconductor region 8 and the N-type semiconductor region 9, the N-type source substrate region 2 has first N independent of each other + body con...

Embodiment 2

[0035] Figure 5 It shows the cell structure of an SJ-pLDMOS device fabricated on a bulk silicon substrate in the present invention. In addition to the P-type substrate 1 and the super-junction surface withstand voltage region 15, this implementation also has a substrate-assisted depletion layer Except for 12, all the other structures are the same as in Example 1.

[0036] Specifically, when the substrate is a P-type lightly doped semiconductor, the conductivity type of the substrate-assisted depletion layer between the substrate and the super-junction surface withstand voltage region is N-type; N-type substrate-assisted depletion The layer in the x direction as shown in the figure is formed of uniformly doped, linearly graded doped or piecewise gradedly doped N-type semiconductors, and its doping concentration gradually decreases from the N-type source substrate region to the P-type drain region.

[0037] Specifically, when the substrate is an N-type lightly doped semiconduc...

Embodiment 3

[0040] Figure 6 A specific embodiment of a pLDMOS device cell fabricated on an SOI substrate is shown in the present invention. This implementation is the same as Embodiment 1 except that the P-type substrate 1 is replaced by an SOI substrate; wherein, The SOI substrate includes a substrate layer 14 and an insulating dielectric layer 13 located on the substrate layer 14. The doping type of the substrate layer 14 can be P-type or N-type, and the P-type substrate layer is selected in this embodiment. .

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Abstract

The invention provides a super junction LDMOS device, which belongs to the technical field of power devices. The cell structure of the super junction LDMOS device of the present invention includes: a substrate, a first active region and a second active region located at both ends of the substrate, and a super junction surface withstand voltage region located between the two active regions; A MOSFET of the first conductivity type is formed on the side close to the first active region and the surface withstand voltage region, and a MOSFET of the second conductivity type is formed on the side adjacent to the second active region and the surface withstand voltage region; In the case of additional control signals, after one type of carrier channel is turned on for conduction, another type of carrier in the superjunction surface withstand voltage region can automatically realize the conduction of another type of carrier, and no conductance modulation effect is formed. Therefore, the present invention ensures rapid turn-off of unipolar devices while significantly enhancing the current capability, and the present invention can integrate two superjunction LDMOSs with different conduction types but similar current capabilities under the same process.

Description

technical field [0001] The invention belongs to the technical field of power semiconductors, and in particular relates to a high-voltage lateral superjunction semiconductor device. Background technique [0002] The miniaturization and integration of power electronic systems is an important research direction of power semiconductor devices. Smart Power Integrated Circuit (SPIC) or High Voltage Integrated Circuit (HVIC) integrates low-voltage circuits such as protection, control, detection, and drive and high-voltage power devices on the same chip, which not only reduces the size of the system volume, improving system reliability. At the same time, in higher frequency working occasions, due to the reduction of system lead inductance, the requirements for buffer and protection circuits can be significantly reduced. [0003] Lateral Double-diffused Metal Oxide Field Effect Transistor (LDMOS) is a key technology of SPIC or HVIC. However, due to the fact that the high-voltage t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L29/78
CPCH01L29/0634H01L29/0692H01L29/7816H01L29/402H01L29/7831
Inventor 易波
Owner 杭州朋声科技有限公司