A method for preparing a semiconductor structure with a porous dielectric layer

Abstract

The invention provides a method of preparing a semiconductor structure having a porous dielectric layer. The method comprises: a lower dielectric layer having interconnect lines is provided; a nitrogen-rich etch stop detection layer, a porous inter-layer dielectric layer, a low-k buffer layer, a metal hard mask layer, and a photoresist layer with an opening pattern are formed on the lower dielectric layer successively; first etching is carried out on the metal hard mask layer and the low-k buffer layer below by using the opening pattern of the photoresist as a mask; the rest of photoresist isremoved; second etching is carried out on the porous inter-layer dielectric layer below by using the opening as a mask, wherein the second etching employs femtosecond laser etching and the edge of theexposed hole structure is melted partially to seal the exposed hole structure when the porous inter-layer dielectric layer is etched by using femtosecond laser; third etching is carried out and hydrogen gas is introduced during the etching; and after exposure of the lower interconnect lines, hydrogen gas is continuously led to obtain an open structure in the porous inter-layer dielectric layer.

Description

technical field [0001] The invention relates to a method for preparing a semiconductor structure, in particular to a method for preparing a semiconductor structure with a porous low-K or ultra-low-K interlayer dielectric layer. Background technique [0002] The rapid development of semiconductor integrated circuit technology constantly puts forward new requirements for the development of interconnection technology. At present, in the back-end process of semiconductor manufacturing, in order to connect the integrated circuits composed of various components, metal materials with relatively high conductivity are usually used, but as the size of semiconductor devices continues to shrink, the interconnection structure becomes narrower and narrower. , resulting in higher and higher interconnect resistances. With the help of copper's excellent electrical conductivity, copper interconnection technology has been widely used in the technology of 90nm and 65nm technology nodes. [00...

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Problems solved by technology

[0004] However, the use of low-K or ultra-low-K insulating dielectric materials poses new requirements for semiconductor manufacturing processes. On the one hand, in order to obtain low-K materials or ultra-low-K materials and reduce the K value of materials, the materials usually used are porous materials. However, the mechanical strength of porous materials is relatively low, which leads to easy damage to the insulating dielectric layer during the process of etching through holes or trenches. On the other hand, the porous insulating dielectric layer is easily infiltrated by external materials, causing pollution , reducing the reliability of the material

Existing academic studies have pointed out that the "open" pore structure exposed to the outside when etching the porous dielectric layer can be formed into a closed structure through an additional "plugging" process, so as to prevent metal impurities from easily forming an interconnection structure. However, the additional process not only increases the cost, but also easily changes the shape of the through hole or trench formed by etching, resulting in a less than ideal effect of the final interconnection structure; and usually Next, there are other interconnection structures under the through holes or trenches formed in the interlayer dielectric layer. During etching, it is easy to cause damage to the underlying interconnection structure, which will affect the stability and reliability of semiconductor devices. Sex makes a big difference

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