A low jitter frequency division clock circuit

Abstract

The present invention provides a low-jitter frequency-division clock circuit, comprising: a clock control signal generation circuit for generating clock signals with different phases; a low-level narrow pulse width clock control signal generation circuit for generating low-level narrow pulse width clock control signal; a high-level narrow pulse width clock control signal generation circuit, used to generate a high level narrow pulse width clock control signal; High-level narrow-pulse-width clocking signal to generate a frequency-divided clock signal; the clock input to the output in the present invention is delayed by at most three logic gates, compared to the traditional ÷2 frequency-divided clock based on D flip-flops The circuit passes through the delay of 6 or more logic gates, and the present invention has fewer logic gates, smaller delay, lower jitter, stable cycle and low jitter characteristics, reduced rising edge and falling edge time, and is beneficial to low jitter characteristics , to ensure that the flip-flop output phase difference is fixed, and has a strong driving capability.

Description

Technical field [0001] The invention relates to the field of electronics, in particular to a low-jitter frequency division clock circuit. Background technique [0002] With the development of 5G communication, Internet of Things and big data technology, the system processing signal bandwidth is getting wider and wider, and the bandwidth of wireless signal reception is getting wider and wider. The instantaneous bandwidth of the A / D converter is required to continuously increase, and then A / D The converter sampling rate is getting higher and higher. Affected by factors such as device characteristic speed, parasitic effects, finite rise time and finite fall time of the clock, the sampling rate of a single-channel A / D converter is always limited. [0003] At present, in order to further improve the sampling rate of A / D converters, one of the mainstream technologies is to use time interleaving technology, which uses multiple channels to alternately and orderly sample, quantize and enco...

AI Technical Summary

Problems solved by technology

The ÷2 frequency division clock circuit often used in digital integrated circuit design is as attached figure 1 as shown, figure 1 In triggers such as figure 2 As shown, the advantage of this kind of flip-flop is that it is simple in structure and easy to implement, but its disadvantages are also obvious. The disadvantages are: first, the main clock fs to ÷2 frequency division output must pass through at least 6 or more logic gates, and the transmission path The noise of each logic gate above contributes to the noise of the output ÷ 2 frequency division clock, and the jitter is relatively large; secondly, the output of each logic gate on the transmission path is easily affected by the power supply noise, which affects the output ÷ 2 frequency division clock Noise contributes, which leads to increased jitter. The output clock of this frequency division circuit is more sensitive to power supply noise. Third, the output drive of this flip-flop is very limited. As the load increases, it must be inserted between the flip-flop output CKOUT and the load. More buffers, further leading to greater jitter on the clock signal at the load

Since the output signal-to-noise ratio of the A / D converter increases with the increase of the analog input frequency and the resolution, the A / D converter has higher and higher requirements on the clock jitter, while the clock generated by the traditional D flip-flop frequency division clock circuit The jitter is large, which can no longer meet the design requirements of high-speed and high-precision A / D converters

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