Method for detecting voids in dielectric layer and method for manufacturing semiconductor device

Abstract

The present invention provides a method for detecting voids in a dielectric layer and a method for manufacturing a semiconductor device. The method for detecting voids in a dielectric layer includes: firstly, providing a substrate with a dielectric layer, the A plurality of conductive contact plugs are formed in the dielectric layer; then, part of the thickness of the dielectric layer is removed to expose the sidewalls of the height of the conductive contact plugs; finally, scanning has all exposed The surface of the substrate of the side wall of the conductive contact plug, to detect whether there is a bridging defect between the side walls of the adjacent conductive contact plug, the position of the bridging defect is the dielectric layer The location where voids are created during deposition. The technical solution of the present invention can quickly and accurately detect the position and quantity of bridging defects in the dielectric layer, so as to obtain the position and quantity of voids in the dielectric layer, thereby accelerating the research and development progress of semiconductor devices And improve the yield rate of semiconductor devices, and ultimately save costs.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for detecting voids in a dielectric layer and a method for manufacturing semiconductor devices. Background technique [0002] In the structure of the chip, the conductive contact plug (CT) in the dielectric layer (ILD) plays a key connection role, and the performance of the conductive contact plug is a key factor affecting the performance of the chip. However, in the actual manufacturing of chips, during the process of depositing the dielectric layer, voids (Void) may be generated in the dielectric layer, and multiple contacts for filling the conductive contact plugs are formed when the dielectric layer is etched. When the holes are formed, the voids generated may cause two or more adjacent contact holes to be connected. When these contact holes are filled with metals such as tungsten, the metal will also fill the voids in the dielectric layer connected to...

AI Technical Summary

Problems solved by technology

[0003] 1. The structural design of the chip: There are usually many MOS field effect transistor structures formed in the dielectric layer of the chip, and generally conductive contact plugs need to be formed on the gate, source and drain of each MOS field effect transistor. However, the gap between the gate and the gate is small, and it is easier to form a void in the gate gap when depositing the dielectric

Therefore, the design of the gap between the gates and the slope angle of the gate sidewall in the structure of the chip may cause voids in the deposited dielectric layer

[0004] 2. The design problem of CVD process: For example, when the deposition speed of the dielectric material set on the CVD machine is too fast, it may cause the dielectric material to be quickly stacked in the gap between the gate and the gate, so that the stacked dielectric material Formation of voids between the electrode and the underlying deposited dielectric

If the chip is in the research and development stage, this process greatly increases the development time of the chip, affects the development progress of new products, and leads to an increase in research and development costs; if the chip has been mass-produced, a large number of abnormal chips containing holes may be produced during this period, thus Leading to a decline in the yield rate of the chip and a serious loss of production costs

In addition, FA analysis uses a limited number of samples, the process is complex, and it is difficult to quantify the exact location and number of conductive contact plug bridging defects (i.e., voids in the dielectric layer)

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