Semiconductor storage device and manufacturing method thereof, and electronic device including storage device

A technology for storage devices and semiconductors, which is applied to semiconductor devices, circuits, electrical components, etc., and can solve problems such as difficulty in stacking multiple vertical devices, high resistance, and difficulty in controlling gate length.

Active Publication Date: 2019-03-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, for vertical devices, it is difficult to control the gate length, especially for single crystal channel materials
On the other hand, if a polycrystalline channel material is used, the channel resistance is greatly increased compared to single crystal material, making it difficult to stack multiple vertical devices, as this would result in an excessively high resistance
[0004] In addition, it is difficult to create a buried bit line under the vertical transistor in the monocrystalline channel layer

Method used

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  • Semiconductor storage device and manufacturing method thereof, and electronic device including storage device
  • Semiconductor storage device and manufacturing method thereof, and electronic device including storage device
  • Semiconductor storage device and manufacturing method thereof, and electronic device including storage device

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Embodiment Construction

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

[0015] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity of presentation. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions / layers with different shapes, s...

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Abstract

The invention discloses a semiconductor storage device and a manufacturing method thereof, and an electronic device including the storage device. According to an embodiment, the semiconductor storagedevice can include a substrate, a storage cell array arranged on the substrate, a plurality of bit lines formed on the substrate, and a plurality of word lines formed on the substrate; storage cells in the storage cell array are arranged in rows and columns; each storage cell includes a vertical extended columnar active area; the columnar active area includes source / drain areas located at the upper and lower ends separately and a channel area located between the source / drain areas, wherein the channel area includes a single crystal semiconductor material; and each storage cell also includes agate stack formed around the periphery of the channel area; each bit line is located at the lower end of the corresponding storage cell column separately, and is electrically connected to the source / drain areas at the lower end of each storage cell in the corresponding column; and each word line is electrically connected to the gate stack of each storage cell in the corresponding storage cell rowseparately.

Description

technical field [0001] The present disclosure relates to the field of semiconductors, and in particular, to a semiconductor memory device based on a vertical type device, a manufacturing method thereof, and an electronic device including such a semiconductor memory device. Background technique [0002] In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the source, gate and drain are arranged in a direction substantially parallel to the surface of the substrate. Due to this arrangement, the horizontal type device cannot be easily further scaled down. Unlike this, in a vertical type device, the source, gate, and drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, vertical devices are easier to scale down than horizontal devices. A nanowire vertical gate-all-around field effect transistor (V-GAAFET, Vertical Gate-all-around Field Effect Transistor) is one of the candidates for future...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11556H01L27/11526H01L27/11582H01L27/11573H10B12/00H10B41/10H10B41/27H10B41/30H10B41/40H10B43/10H10B43/27H10B43/30H10B43/40H10B51/10H10B51/20H10B51/30
CPCH10B41/40H10B41/27H10B43/40H10B43/27H01L29/78642H01L29/66666H01L27/1203H01L29/7391H01L29/7827H01L29/42356H10B12/315H10B12/0335H10B12/05H10B12/482H10B12/30H10B41/10H10B41/30H10B43/10H10B43/30H10B51/10H10B51/20H10B51/30
Inventor 朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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