Bonding structure and forming method thereof

Abstract

The invention relates to a bonding structure and a forming method thereof. The forming method comprises the steps of providing two substrates, wherein each substrate comprises a dielectric layer and ametal interconnection part formed on the surface of the exposed top in the dielectric layer; forming blocking layers on the surfaces of the metal interconnection parts at relative bonding positions of the two substrates, and forming a blocking layer on the surface of the top of the metal interconnection part with a greater dimension at least when the metal interconnection parts are arranged at both the relative bonding positions of the two substrates, wherein the blocking layer is made of a conductive material and can prevent the diffusion of metal atoms; bonding the surfaces of the two substrates relatively, wherein the blocking layer is located between the metal interconnection parts of the two substrates. The blocking layer can prevent diffusion of the metal atoms in the metal interconnection parts to adjacent dielectric layers, so that the phenomenon that the electrical performance of the device is reduced and the reliability is poor due to metal atom diffusion is avoided, and thereliability of the bonding device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a bonding structure and a forming method thereof. Background technique [0002] In recent years, the development of flash memory (Flash Memory) is particularly rapid. The main feature of flash memory is that it can keep stored information for a long time without power on, and has the advantages of high integration, fast access speed, easy erasing and rewriting, etc. Has been widely used. In order to further increase the bit density (Bit Density) of the flash memory and reduce the bit cost (Bit Cost), three-dimensional flash memory (3D NAND) technology has been developed rapidly. [0003] The 3D NAND flash memory structure includes a memory array structure and a CMOS circuit structure above the memory array structure. The memory array junction and the CMOS circuit structure are usually formed on two different wafers, and then bonded to The CMOS circuit wafer and the stor...

AI Technical Summary

Problems solved by technology

[0004] However, in the prior art, at the bonding surface of the metal interconnection between the memory array structure and the CMOS circuit structure, metal atoms are prone to diffusion and electromigration during the heating and cooling process of the bonding process and after bonding, so that the metal bond Pores are generated in the joint surface, resulting in leakage, shortened electromigration life, etc., which reduces the reliability of the product

In the prior art, in order to reduce the above problems, it is necessary to perform many adjustments and reliability control on the chemical mechanical polishing process for forming the metal interconnection, resulting in an increase in cost

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