Semiconductor device and manufacturing method thereof, and electronic device
A manufacturing method and semiconductor technology, applied in semiconductor devices, electric solid devices, circuits, etc., can solve the problems of inconsistent hole size, large capacitive coupling effect, poor consistency of adjacent word lines, etc., so as to reduce word line interference and improve device performance. performance, the effect of reducing the dielectric constant
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Embodiment 1
[0062] The following will refer to Figure 2A ~ Figure 2J A method for fabricating a semiconductor device according to an embodiment of the present invention will be described in detail.
[0063] First, if Figure 2A As shown, a semiconductor substrate 200 is provided. The semiconductor substrate 200 at least includes a core region 200A and a peripheral region 200B. Memory cells and select gates SG are formed on the core region 200A of the semiconductor substrate 200. In the semiconductor substrate 200 A logic gate Gate is formed in the peripheral region 200B of the substrate 200 , and a first protection layer 205 is formed on the surface of the semiconductor substrate 200 , the memory cells, the selection gate SG and the logic gate Gate. The memory cell includes a floating gate 201 , an isolation layer 202 , a control gate 203 and a hard mask layer 204 stacked in sequence, and the control gate is connected to the word line WL. The selection gate SG and the logic gate Gate a...
Embodiment 2
[0097] The present invention also provides a semiconductor device, such as image 3 As shown, the semiconductor device includes: a semiconductor substrate 300, the semiconductor substrate 300 at least includes a core region 300A and a peripheral region 300B, memory cells and select gates are formed on the core region 300A of the semiconductor substrate 300, and A logic gate is formed on the peripheral region 300B of the semiconductor substrate 300, and the memory cell includes a floating gate 301, an isolation layer 302, a control gate 303, and a silicide 304 stacked in sequence; A spacer 305 is formed on the sidewall of the gate; an interlayer dielectric layer 306, the interlayer dielectric layer 306 covers the top of the memory cell, the select gate, the logic gate and the semiconductor substrate; wherein, An air gap 307 is formed between the adjacent storage units, and the air gap 307 is at least surrounded by the adjacent storage units and the interlayer dielectric layer 3...
Embodiment 3
[0106] Still another embodiment of the present invention provides an electronic device, including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, the semiconductor device includes: a semiconductor substrate, the semiconductor substrate at least includes a core area and a peripheral area, a memory cell and a selection gate are formed on the core area of the semiconductor substrate, and a A logic gate is formed on the region, and the memory cell includes a floating gate, an isolation layer and a control gate stacked in sequence; a spacer is formed on the sidewall of the selection gate and the logic gate; an interlayer dielectric layer, the The interlayer dielectric layer covers the top of the memory cell, the select gate, the logic gate, and the semiconductor substrate; wherein, an air gap is formed between adjacent memory cells, and the air gap is at least Surrounded by the adjacent memory cells and the dielectric layer.
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