Semiconductor structure and forming method thereof

A semiconductor and annular groove technology, applied in the fields of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problem of the sealing performance of the chip sealing ring needs to be improved, to prevent corrosion, avoid stress damage, improve The effect of protection

Inactive Publication Date: 2019-07-19
HUAIAN IMAGING DEVICE MFGR CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, the sealing performance of the chip sealing ring in the prior art still needs to be improved

Method used

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  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

Examples

Experimental program
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Effect test

no. 1 example

[0031] Figure 1 to Figure 7 This is a schematic diagram of the structure corresponding to each step of the semiconductor structure forming method in this embodiment.

[0032] reference figure 1 , A semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a device region II and a sealing region I surrounding the device region II. The semiconductor substrate 100 has a first surface 101 and a first surface 101 opposite to the first surface 101. The second surface 102.

[0033] The material of the semiconductor substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. In this embodiment, the substrate 100 is a silicon substrate.

[0034] reference figure 2 , The front side process is performed on the semiconductor substrate 100, that is, a number of isolation trench (STI) components 120 are formed in the s...

no. 2 example

[0061] The difference between this embodiment and the first embodiment is only the difference in the annular groove, so the steps before forming the annular groove are as in the first embodiment Figure 1 to 4 , I won’t repeat it here. Figure 8 to Figure 12 This embodiment provides a schematic diagram of some steps of the method for forming a semiconductor structure.

[0062] reference Figure 8 , A patterned layer 600 is formed on the surface of the dielectric layer 500.

[0063] Specifically, the patterned layer 600 of the sealing area I has a first opening 601, and the patterned layer 600 of the device area II has a second opening 602.

[0064] In this embodiment, the material of the patterned layer 600 is silicon nitride.

[0065] In other embodiments, the material of the patterned layer 600 may also be silicon oxide.

[0066] reference Picture 9 , Using the patterned layer 600 as a mask to etch the dielectric layer 500 and the semiconductor substrate 100 to form a groove penetra...

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Abstract

The invention relates to a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a device region and a sealing region surrounding the device region, and the semiconductor substrate has a first surface and a second surface opposite to the first surface; forming a sealing ringon the first surface of the semiconductor substrate in the sealing region, and forming a semiconductor device on the first surface of the semiconductor substrate in the device region; etching the second surface of the semiconductor substrate, forming a device region through hole penetrating through the thickness of the semiconductor substrate in the device region, and meanwhile forming an annulargroove penetrating through the thickness of the semiconductor substrate in the sealing region; and filling the device region through hole and the annular groove with conductive layers. The annular groove is formed and filled with the conductive layer, so that the stress damage of the outside to the device region in a chip can be avoided, the erosion of external moisture or corrosive gas can be prevented, and the capability of protecting the device in the chip can be improved.

Description

Technical field [0001] The present invention relates to the field of semiconductors, in particular to a semiconductor structure and a method of forming the same. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, people's requirements for integrated circuit integration and performance have become higher and higher. There is a chip sealing area between the scribe line of each chip on the wafer and the peripheral region of the integrated circuit, which is usually called a chip sealing ring. The chip sealing ring is made up of a dielectric layer and a metal layer. Stacked structure, and the metal layer utilizes dielectric holes passing through the dielectric layer for internal interconnection. When the wafer dicing process is performed along the scribe lane, the sealing ring of the chip can block the stress cracking between the dicing lane and the integrated circuit caused by the wafer dicing process; and the chip sealing r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L23/48
CPCH01L21/76898H01L23/481H01L2224/18
Inventor 管斌张东亮陈世杰黄晓橹
Owner HUAIAN IMAGING DEVICE MFGR CORP
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