A dual-die device with terminal trench structure and method of making the same

A technology of terminal grooves and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as chip failure and affecting device performance, reduce reverse leakage current, improve UIS capability, and prevent lead-in general effect

Active Publication Date: 2019-10-15
NANJING HRM SEMICON CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the reverse type, a surface conduction channel will be formed between the active area and the scribe groove, which will seriously affect the performance of the device and even cause the chip to fail.
From the actual chip manufacturing experience, the phenomenon that the inversion of the silicon surface leads to the formation of surface conductive channels is very common and common, and the existence of surface conductive channels cannot be ignored. Therefore, further improvement is needed.

Method used

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  • A dual-die device with terminal trench structure and method of making the same
  • A dual-die device with terminal trench structure and method of making the same
  • A dual-die device with terminal trench structure and method of making the same

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Embodiment Construction

[0037] The present invention will be further illustrated below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented on the premise of the technical solution of the present invention. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0038] combine Figures 1 to 9 , The embodiment of the present invention provides a method for manufacturing a dual-die device with a terminal trench structure, comprising the following steps:

[0039] Step 1: If figure 1 As shown, a substrate 1 of the first conductivity type is provided, and an epitaxial layer 2 is formed on the upper side of the substrate 1 . Wherein, the substrate 1 is heavily doped, and the epitaxial layer 2 is lightly doped with the first conductivity type.

[0040] Step 2: Etching and forming several first trenches 6 , second trenches 7 and third trenches 8 disp...

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Abstract

The invention discloses a double-tube-core device with a terminal groove structure and a manufacturing method thereof. According to the invention, when a drain electrode is pressurized, a P-body region and an N-epitaxial layer form a depletion layer and is up to a terminal, the breakdown voltage of the whole terminal structure is improved through a terminal trench gate oxide withstand voltage, andthe purpose of reducing the reverse leakage current of the device is achieved. The P-body region is an overall structure, and the upper side of the gate oxide layer is not required to be coated withglue for photoetching before the P-body region is manufactured. A connecting hole is manufactured by two steps, when the connecting hole is etched under second mixed gas, a protective film formed by the second mixed gas is relatively thin, and then the second connecting hole is set to be circular or elliptical, after hole injection and diffusion are carried out, a formed contact area is crescent,the distribution area of the contact area is wider, the reduction of base resistance is facilitated, the conduction of a parasitic triode is prevented, the UIS capacity is further improved, and the effect is remarkable. According to the above-mentioned improvement, the breakdown voltage of the double-tube-core device can be improved by about 8 percent, and the on-resistance can be reduced by 0.6 percent.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a dual-pipe-core device with a terminal groove structure and a manufacturing method thereof. Background technique [0002] In some lithium battery charge and discharge protection circuits, two identical NMOSs are usually used together to realize battery protection functions under overcharge, overdischarge, overcurrent, short circuit, etc. [0003] The conventional practice is to package two NMOSs with their own terminal structures, and then package them together. The disadvantage of this is that the packaged chip has a larger area. [0004] Later, some dual-die devices appeared, such as the dual-die devices disclosed in application numbers 201510683826.7 and 201510683582.2, which only use one terminal for two dies to reduce the area of ​​the chip. The dual-die devices disclosed in application number 201510683582.2 The device also sets a metal layer on the upper side of the terminal...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/088H01L21/8234H01L29/06H01L29/423
CPCH01L21/823437H01L27/088H01L29/0611H01L29/4236
Inventor 张雨陈虞平胡兴正刘海波
Owner NANJING HRM SEMICON CO LTD
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