Method for manufacturing semiconductor device
A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as difficulty in meeting FinFET device manufacturing, and achieve the effects of avoiding process damage, ensuring quality, and improving device performance.
Active Publication Date: 2019-12-13
SEMICON MFG INT TIANJIN +1
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Problems solved by technology
However, the current manufacturing method of high-K metal gate structure is difficult to meet the requirements of smaller size and higher performance FinFET devices.
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[0034] A Complementary Metal-Oxide-Semiconductor (CMOS) is one of the basic semiconductor devices constituting an integrated circuit. The complementary metal-oxide-semiconductor transistor includes: a P-type metal-oxide-semiconductor (PMOS) transistor and an N-type metal-oxide-semiconductor (NMOS) transistor. In the prior art, in order to control the short channel effect while reducing the gate size, the Gate Last (Gate Last) process is usually used to manufacture FinFET devices with a high K metal gate (HKMG, High K Metal Gate), that is, a high K dielectric is used The material replaces conventional materials such as silicon oxide as the gate dielectric layer of the transistor, and uses metal materials instead of conventional materials such as polysilicon as the gate electrode layer of the transistor. Moreover, in order to adjust the threshold voltage of the PMOS transistor and the NMOS transistor, a work function layer (work function layer) is generally formed on the surface...
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The invention provides a method for manufacturing a semiconductor device. The method comprises: firstly, forming a first dummy gate structure and a second dummy gate structure with different top surface heights in a first region and a second region; then, protecting the first dummy gate structure with the lower top surface height by an interlayer dielectric layer, and replacing the second virtualgate structure with a second metal gate structure; lowering the top surface height of the second virtual gate structure by a chemical-mechanical planarization process until the first dummy gate structure is exposed, so that the first dummy gate structure can be replaced with the first metal gate structure. The method of the present invention avoids a photolithography process and an etching processduring the formation of original different work function layers, so that the formation processes of the first metal gate structure and the second metal gate structure are independent of each other, cannot cause additional process damage to the respective semiconductor substrate regions where the first metal gate structure and the second metal gate structure are located, and improve the performance of the finally obtained semiconductor device.
Description
technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for manufacturing a semiconductor device. Background technique [0002] FinFET (Fin Field Effect Transistor) device is an advanced semiconductor device used in 22nm and below process nodes, which can effectively control the insurmountable short channel effect caused by scaling down the device, and it can realize the reduction of the gate of the device Its structure generally includes a fin (Fin) protruding from the surface of the semiconductor substrate, a gate stack structure covering part of the top surface and / or sidewall of the fin (channel region), and a gate stack structure located on the gate The source and drain regions in the fins on both sides of the stack structure. Compared with planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices, FinFET devices can increase the drive current while maintaining a very low off-curr...
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Patent Timeline
Login to View More IPC IPC(8): H01L21/8234H01L21/8238
CPCH01L21/823431H01L21/82345H01L21/823821H01L21/823842
Inventor 张海洋钟伯琛
Owner SEMICON MFG INT TIANJIN