Unlock instant, AI-driven research and patent intelligence for your innovation.

Semiconductor vertical wiring structure and method

A semiconductor and conductor chip technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components and other directions, can solve problems such as affecting the flatness of the front-layer base layer, peeling, affecting the electrical signal transmission performance of the conductive layer, etc. Achieve the effect of improving flatness and risk of peeling, eliminating damage, and improving electrical signal transmission performance

Pending Publication Date: 2020-02-18
SJ SEMICON JIANGYIN CORP
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor vertical wire bonding structure and method, which is used to solve the problem that the existing vertical wire bonding process affects the flatness of the front layer of the base layer and causes peeling after plastic molding. And affect the electrical signal transmission performance of the conductive layer

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor vertical wiring structure and method
  • Semiconductor vertical wiring structure and method
  • Semiconductor vertical wiring structure and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0057] The present invention provides a semiconductor vertical wiring structure, please refer to figure 1 , showing a schematic diagram of the semiconductor vertical wire bonding structure, the semiconductor vertical wire bonding structure includes a semiconductor chip 1, a wire bonding pad 4, a vertical conductive column 9 and a dummy pad 5, wherein the surface of the semiconductor chip 1 has a discrete arrangement The first soldering point and the second soldering point, the wire bonding pad 4 is located at the first soldering point, connected to the internal functional device of the semiconductor chip 1, and the vertical conductive column 9 is connected to the bonding wire On the surface of the welding pad 4 , the dummy welding pad 5 is located at the second welding point for providing a tangential line platform for the formation of the vertical conductive pillar 9 .

[0058]Specifically, the semiconductor chip 1 refers to a semiconductor device that can realize a certain f...

Embodiment 2

[0067] The present invention also provides a semiconductor vertical wiring method, please refer to figure 2 , is shown as a process flow diagram of the semiconductor vertical bonding method, including the following steps:

[0068] First perform step S1: see image 3 , providing a semiconductor chip 1, the surface of the semiconductor chip 1 has a first soldering point and a second soldering point that are separately arranged, and the first soldering point is provided with a wire bonding connected to the internal functional device of the semiconductor chip 1 Pad 4, a dummy pad 5 is provided at the second soldering point.

[0069] Specifically, the semiconductor chip 1 refers to a semiconductor device that can realize a certain function and is manufactured by performing semiconductor processes such as etching and wiring on a semiconductor sheet. The semiconductor chip 1 may have multiple connection points that need to be led out, so the number of the bonding pads 4 may be mul...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
Thicknessaaaaaaaaaa
Login to View More

Abstract

The invention provides a semiconductor vertical wiring structure and method. The method comprises the following steps: S1: providing a semiconductor chip, wherein the surface of the semiconductor chipis provided with a first solder spot and a second solder spot which are arranged separately, the first solder spot is provided with a wiring solder pad connected with the internal functional device of the semiconductor chip and the second solder spot is provided with a virtual solder pad; and S2: wiring is performed on the wiring solder pad, wire cutting is performed on the virtual solder pad andwire is pulled above the wiring solder pad so that the metal wire is broken at the cut point and a vertical conductive column connected with the wiring solder pad is obtained. The virtual solder padis additionally arranged on the second solder spot to eliminate the damage caused by the second solder spot on the front layer in the vertical wiring process so as to improve the flatness of the frontbase layer of the vertical wiring process and the risk of stripping, improve the electrical signal transmission performance of each conductive layer in the chip and improve the efficiency and the accuracy of the vertical wiring process.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, and relates to a semiconductor vertical wiring structure and method. Background technique [0002] All computing and communication systems require power delivery subsystems. Power delivery systems convert the high voltage of a power supply to the many different low voltages required by the discrete devices in the system. In fan-out packaging, the wires that connect all the layers to transmit the power signal determine the magnitude of the signal transmission loss. [0003] In the existing vertical wire bonding process, the wire bonding is performed at the first solder point, and the tangent is performed at the second solder point. Since there is no dedicated pad at the second solder point, the tangent action of the second solder point is in the front Finishing on the PI / metal layer will cause damage to the previous layer and form multiple pits. Due to the uneven surface caused by multipl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/48H01L23/31H01L23/49
CPCH01L21/4821H01L23/3114H01L23/49H01L2224/78301
Inventor 黄晗林正忠陈彦亨吴政达
Owner SJ SEMICON JIANGYIN CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com