A chip interconnection structure of different dimensions and its preparation method
An interconnect structure and chip technology, applied in semiconductor/solid-state device manufacturing, nanotechnology for materials and surface science, semiconductor/solid-state device components, etc., can solve the problem of reducing gas, reduce chip size, limit Application fields and other issues, to achieve the effect of avoiding solvent volatilization, increasing solvent volatilization, and small porosity
Active Publication Date: 2022-01-25
SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
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Problems solved by technology
[0004] However, in the chip packaging interconnection scheme in the prior art, the limited space of the metal paste in the process of connecting the chip and the substrate makes it difficult to transport the reducing gas in, and it is difficult for the organic matter to volatilize, especially for large-sized chips, the excess organic matter Residues in the solder layer will affect the electrical conductivity, thermal conductivity, porosity and other properties of the solder layer
In order to avoid this phenomenon, the current technology will reduce the chip size, which limits its more application fields.
Method used
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Embodiment 1
[0035] According to an embodiment of the present invention, a method for preparing a chip interconnection structure with different dimensions and sizes is as follows:
[0036]Step 1: 42 parts by mass of nano-copper particles (particle size 100nm) and 21 parts by mass of copper nanorods (particle size 80nm, length 1um) were treated with ascorbic acid, and the mass ratio of copper powder to ascorbic acid was 1:6.
[0037] Step 2: Put 7 parts of quality nickel nanowires (50nm in particle size and 1um in length), 15 parts of quality isopropanol, 5 parts of quality terpineol, and 2 parts of quality polyvinyl butyral into a mechanical mixer for mixing and stirring , In addition, add 2 parts of quality polyvinyl alcohol and lauric acid respectively.
[0038] Step 3: Mix the ascorbic acid-washed nano-copper particles and copper nano-rods evenly, and then put them into a blender and stir with a solvent for 2 hours. After stirring evenly, put it into a ball mill to grind for 12 hours, ...
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Abstract
The invention discloses a chip interconnection structure of different dimensions and a preparation method thereof, comprising: a chip; a substrate; a nanometer metal interconnection region, the nanometer metal interconnection region includes a first region and a second region, and the first The area includes nano metal wires and / or first nano metal particles with different heights; the second area includes nano metal paste, and the nano metal paste includes a mixture of second nano metal particles and nano metal rods, and the second area A channel is defined by the nano metal wires and first nano metal particles of different heights in the first region and the nano metal paste in the second region. The chip interconnection structure of the present invention uses nano-metal paste to be arranged in different regions, which can effectively increase solvent volatilization and effectively avoid solvent volatilization caused by excessive chip size. It is prepared by this multi-dimensional mixed nano-copper powder Nano-copper paste has a small porosity, which improves the electrical and thermal conductivity of the sintered layer.
Description
technical field [0001] The invention relates to the field of chip interconnection packaging, in particular to a chip interconnection structure of different dimensions and a preparation method thereof. Background technique [0002] With the rapid development and application of wide bandgap semiconductors such as gallium nitride and silicon carbide in the power electronics industry, the packaging and interconnection industry also needs to be continuously improved. The maximum operating temperature of current high-power devices has exceeded 300°C, which requires packaging and interconnection materials with higher melting points. [0003] Traditional lead solder cannot meet the wide application of high-power electronic devices due to its low melting point, lower than 200 °C. Recently, it is one of the major trends to use the mixture of metal particles and organic solvents as the material for advanced packaging and interconnection. Among them, the metal block has a very high me...
Claims
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IPC IPC(8): H01L23/488H01L21/60B82Y30/00B82Y40/00
CPCH01L24/32H01L24/33H01L24/83B82Y30/00B82Y40/00H01L2224/32052H01L2224/32225H01L2224/3312H01L2224/83024
Inventor 周荃刘起鹏钱靖叶怀宇张国旗
Owner SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA