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Method for thinning silicon wafer

A silicon wafer and silicon wafer surface technology, applied in the field of thinning silicon wafers, can solve problems affecting production, large warpage, hidden cracks, etc., and achieve the effects of increasing the ratio, reducing warpage, and increasing surface tension

Active Publication Date: 2020-07-10
GTA SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is to overcome the defects in the prior art that the silicon wafer warps too much when it is thinned to a certain extent, which easily causes fragments or cracks in the subsequent processing and affects subsequent production, and provides a Method for Thinning Silicon Wafers with Improved Warpage

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  • Method for thinning silicon wafer

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Embodiment Construction

[0015] The present invention will be further described below by means of a preferred embodiment, but the present invention is not limited to the scope of the described embodiment.

[0016] This embodiment provides a method for thinning a silicon wafer, referring to figure 2 , the method for thinning the silicon wafer of the present embodiment comprises the following steps:

[0017] Step S101 , growing a passivation layer.

[0018] The passivation process is to cover the surface of the polished silicon wafer with a protective dielectric film to prevent the surface contamination of the silicon wafer. The commonly used medium is a thermally grown silicon dioxide film.

[0019] Step S102 , passivation layer photolithography, in this step, the part of the passivation layer mask corresponding to the scribe lane area on the surface of the silicon wafer is defined as opaque.

[0020] The passivation layer photolithography step generally includes photoresist coating, passivation lay...

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Abstract

The invention discloses a method for thinning a silicon wafer, and the methodcomprises the steps of passivation layer photoetching and passivation layer etching;in the passivation layer photoetching step, the part, corresponding to a scribing channel region on the surface of the silicon wafer, of a passivation layer photomask plate is defined to be lightproof, so that the scribing channel region on the surface of the silicon wafer in the passivation layer etching step is covered with photoresist, wherein the photoresist is used for preventing the scribing channel region on the surface of the silicon wafer from being etched in the etching process of the passivation layer. Therefore, the thickness of the passivation layer in the latticed scribing channel area on the surface of the silicon wafer after the passivation layer etching step is increased, the surface tension of the silicon wafer is increased, the stress of the thinned silicon wafer is further balanced, the warping degree of thethinned silicon wafer is effectively reduced, and the requirements of subsequent production are met.

Description

technical field [0001] The invention belongs to the technical field of semiconductor device manufacturing, and in particular relates to a method for thinning a silicon chip. Background technique [0002] In the manufacturing process of semiconductor devices, after cutting and polishing silicon wafers, generally such figure 1 The production process shown in the sequence includes the steps of growing a passivation layer on the surface of the silicon wafer, photolithography of the passivation layer, etching of the passivation layer, grinding the back with coarse sand, grinding the back with fine sand, cleaning, evaporating gold on the back, and encapsulating. Usually, when the silicon wafer is thinned to less than 140 microns, there will be a large bending due to stress. Under the action of gravity, the warpage of the thinned silicon wafer can exceed 10mm, which will easily cause silicon wafer fragments or cracks in the subsequent processing process, which will affect the subs...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02
CPCH01L21/02008H01L21/02013H01L21/02016H01L21/02019Y02P70/50
Inventor 刘峰松吴正泉
Owner GTA SEMICON CO LTD
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