N-type FET and manufacturing method thereof

A manufacturing method, N-type technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as inability to further reduce device leakage and conflicts in doping control requirements, and achieve great application prospects and commercial value. Reduce subthreshold leakage current and simple process

Active Publication Date: 2020-07-28
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There is a contradiction between reducing the leakage current corresponding to I1 and I2 and the leakage current corresponding to I3 and I4 in existing devices, that

Method used

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  • N-type FET and manufacturing method thereof
  • N-type FET and manufacturing method thereof
  • N-type FET and manufacturing method thereof

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Embodiment Construction

[0071] Such as Figure 4 As shown, it is a schematic diagram of the structure of the N-type FET of the embodiment of the present invention; the N-type FET of the embodiment of the present invention includes a gate structure, a spacer 7, a lightly doped drain region 5, a source region 8, a drain region 9 and a halo implantation region 6.

[0072] The gate structure is formed on the surface of the semiconductor substrate 1 . Field oxygen 2 is also formed on the semiconductor substrate 1, and the field oxygen 2 isolates an active region.

[0073] In the embodiment of the present invention, a P-type well is formed on the semiconductor substrate 1, the formation region of the NFET is located in the formation region of the P-type well, and the gate structure is formed in the P-type well On the surface.

[0074] The semiconductor substrate 1 includes a silicon substrate.

[0075] The gate structure includes a gate dielectric layer 3 and a gate conductive material layer 4 stacked ...

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Abstract

The invention discloses an N-type FET. A halo implantation region is located at the bottom of a lightly doped drain region and wraps the lightly doped drain region; an N-type FET has an optimized structure for reducing leakage current, and the optimized structure is characterized in that doped impurities of the halo implantation region are composed of BF2 and carbon which are doped by adopting a common ion implantation process; the doped impurity of the lightly doped drain region is arsenic; the doping concentration and the doping depth of BF2 in the halo ring injection region are provided with a first setting structure, and the arsenic doping concentration of the lightly doped drain region is provided with a second setting structure; under the condition of ensuring that the turn-on current of the NFET meets the target value, the doping concentration of BF2 is reduced and the doping depth of BF2 is increased in the first setting structure, and the doping concentration of arsenic is reduced in the second setting structure and carbon doping of the halo implantation region is combined to maintain or reduce the sub-threshold electric leakage current. The invention further discloses a manufacturing method of the N-type FET. According to the invention, sub-threshold leakage current and junction leakage current of the device can be reduced at the same time, and extremely low electricleakage is realized.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an N-type FET. The invention also relates to a manufacturing method of NFET. Background technique [0002] As the size of semiconductor devices continues to shrink, the short-channel effect of devices becomes more and more obvious, making the leakage of devices more and more difficult to control. Especially when the process node enters the nanometer scale, the threshold voltage (Vt) of the device rolls down (roll-off) strongly, making it difficult to control the subthreshold leakage. Although increasing the amount of halo ion implantation can alleviate the problem of subthreshold leakage to a certain extent, a new problem of high leakage at the P-N junction will be introduced when the implant amount is high, resulting in extreme The development of low-leakage components has encountered serious obstacles. [0003] Such as figure 1 Shown is a schema...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/167H01L29/36H01L21/336
CPCH01L29/7833H01L29/7838H01L29/0607H01L29/0684H01L29/167H01L29/36H01L29/66492H01L29/66575Y02P70/50
Inventor 白文琦王世铭黄志森胡展源李昆鸿
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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