Isolation capacitor and preparation method thereof

Abstract

The invention discloses an isolation capacitor and a preparation method thereof. The isolation capacitor comprises a substrate, a first electrode plate and a second electrode plate located on the substrate, and a dielectric layer located between the first electrode plate and the second electrode plate, at least part of the area on the substrate is a shallow groove isolation area, and a plurality of air holes are formed in the shallow groove isolation area. According to the isolation capacitor, the average dielectric constant of the shallow trench isolation area is reduced by adopting an air hole filling scheme such that the capacitance value of a parasitic capacitor CP is reduced; the preparation process of the isolation capacitor is completely compatible with a traditional CMOS process, an illumination mask etching process is not added, extra cost is not increased, and the design difficulty of a high-voltage isolation circuit is reduced.

Description

technical field [0001] The invention belongs to the technical field of data isolation, and in particular relates to an isolation capacitor and a preparation method thereof. Background technique [0002] Digital isolators have a very wide range of application requirements, because in the harsh motor application environment, the application not only needs to be able to resist high-voltage transients, prevent data from being disturbed and distorted, but also need to eliminate the impact of high voltage on the life of the isolator. There are currently three isolation methods on the market: optical coupling isolation, magnetic coupling isolation, and high-voltage capacitive isolation. Among them, high-voltage capacitive isolation has low cost, low power consumption, high temperature resistance, long service life, and is not affected by external magnetic fields. It is easy to integrate into traditional The CMOS process has many advantages and has received widespread attention. Mor...

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Problems solved by technology

[0005] 1. Place the lower plate on the upper metal, thereby reducing the parasitic capacitance from the lower plate to the substrate, but this will add at least two layers of photomask (mask) process, which greatly increases the process cost;

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