Hardware programmable heterogeneous multi-core system-on-chip

Abstract

The invention discloses a hardware programmable heterogeneous multi-core system-on-chip, and belongs to the technical field of integrated circuits. According to the system-on-chip, a multi-core DSP, amulti-core MPU, a GPU, an FPGA and a plurality of IP components are organically combined together through an on-chip high-speed bus interconnection network to form a hardware-programmable and processor-multi-core heterogeneous system-on-chip chip, and the specialty of each heterogeneous core is brought into full play. Through an area formed by the multi-core DSP and the FPGA, services such as high-throughput-rate data preprocessing, dense data operation and a bottom-layer algorithm are realized; and an area formed by the multi-core MPU, the GPU and the FPGA accelerator is used for achieving services such as a user interface, a high-level algorithm, application program running and network transmission. The FPGA can also realize a hardware acceleration function required in a multi-core DSPand a multi-core MPU. Based on hardware reconfiguration, the chip architecture improves the flexibility of system-on-chip integration and the expandability and upgradability of later products.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a hardware-programmable heterogeneous multi-core system on chip. Background technique [0002] At present, applications such as communication, machine vision, assisted driving, medical / biological imaging, avionics, big data analysis, and the Internet of Things all require high-performance digital signal processing, intensive data computing capabilities, and strong graphics and image processing and display functions. In addition, systems and algorithms are required to be flexible and self-adaptive. Now that the update speed of the whole machine system is accelerating, the whole machine system should have certain upgrade capabilities. This requires that after the product is manufactured, the chips in the system can provide certain modification, optimization and reconfiguration capabilities. [0003] In order to meet the above demands, the industry has made many attempt...

AI Technical Summary

Problems solved by technology

[0007] After searching the existing technical literature, it is found that the patent invention with the application number 201410273439.1 and the title "Heterogeneous multi-core processor and task scheduling method based on ARM, DSP and FPGA" discloses a heterogeneous multi-core processor technology. The same kind of processors in the scheme do not adopt multi-core structure, and the interconnection between heterogeneous processors adopts PCI peripheral interconnection bus or simple bus network, which cannot solve the bottleneck problem of the current SOC storage interface and bus, and does not propose a programmable accelerator function. Its capacity for intensive data processing and practical application needs to be strengthened

The patent invention with application number 201110008399.4 and titled "Multi-core DSP Reconfigurable ASIC System" discloses a multi-core DSP reconfigurable ASIC system used in the field of digital signal processing technology, with multi-core DSP as the operation core, According to different execution tasks, the interconnection topology between DSPs is realized by FPGA. The operation data of multi-core DSP is obtained by the control processor through the memory interface and transmitted to DSP. The task scheduling and control of multi-core DSP is implemented by the central processing unit; Its shortcoming is that the interconnection topology between multi-core DSPs performs hardware interconnection according to the requirements of the algorithm operation process. In this way, the interconnection topology participates in the operation. Although the assignment of DSP task blocks is relatively clear, the application adaptability is slightly poor. It is not convenient for the expansion of DSP multi-core, and it is inconvenient for the flexible scheduling between DSP multi-core. In addition, the task scheduling of multi-core DSP needs to be controlled by the central processing unit. The application of the reconfigurable ASIC system still focuses on signal processing and underlying data. deal with

Images