A hardware programmable heterogeneous multi -core film system

Abstract

The invention discloses a hardware-programmable heterogeneous multi-core on-chip system, which belongs to the technical field of integrated circuits. The system-on-chip organically combines multi-core DSP, multi-core MPU, GPU, FPGA, and numerous IP components through the on-chip high-speed bus interconnection network to form a hardware-programmable, multi-core heterogeneous system-on-chip chip. Specialization for each heterogeneous core. In the present invention, the area composed of multi-core DSP and FPGA is used to complete the realization of high-throughput data preprocessing, intensive data calculation, and bottom-level algorithms; the area composed of multi-core MPU, GPU, and FPGA accelerator is used to complete the user interface, high-level Realization of algorithms, application program operation, network transmission and other services. And the FPGA can also realize the hardware acceleration function required in the multi-core DSP and multi-core MPU. Based on hardware reconfigurability, the chip architecture improves the flexibility of system-on-chip integration, and the scalability and upgradeability of later products.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a hardware-programmable heterogeneous multi-core system on chip. Background technique [0002] At present, applications such as communication, machine vision, assisted driving, medical / biological imaging, avionics, big data analysis, and the Internet of Things all require high-performance digital signal processing, intensive data computing capabilities, and strong graphics and image processing and display functions. In addition, systems and algorithms are required to be flexible and self-adaptive. Now that the update speed of the whole machine system is accelerating, the whole machine system should have certain upgrade capabilities. This requires that after the product is manufactured, the chips in the system can provide certain modification, optimization and reconfiguration capabilities. [0003] In order to meet the above demands, the industry has made many attempt...

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Problems solved by technology

[0007] After searching the existing technical literature, it is found that the patent invention with the application number 201410273439.1 and the title "Heterogeneous multi-core processor and task scheduling method based on ARM, DSP and FPGA" discloses a heterogeneous multi-core processor technology. The same kind of processors in the scheme do not adopt multi-core structure, and the interconnection between heterogeneous processors adopts PCI peripheral interconnection bus or simple bus network, which cannot solve the bottleneck problem of the current SOC storage interface and bus, and does not propose a programmable accelerator function. Its capacity for intensive data processing and practical application needs to be strengthened

The patent invention with application number 201110008399.4 and titled "Multi-core DSP Reconfigurable ASIC System" discloses a multi-core DSP reconfigurable ASIC system used in the field of digital signal processing technology, with multi-core DSP as the operation core, According to different execution tasks, the interconnection topology between DSPs is realized by FPGA. The operation data of multi-core DSP is obtained by the control processor through the memory interface and transmitted to DSP. The task scheduling and control of multi-core DSP is implemented by the central processing unit; Its shortcoming is that the interconnection topology between multi-core DSPs performs hardware interconnection according to the requirements of the algorithm operation process. In this way, the interconnection topology participates in the operation. Although the assignment of DSP task blocks is relatively clear, the application adaptability is slightly poor. It is not convenient for the expansion of DSP multi-core, and it is inconvenient for the flexible scheduling between DSP multi-core. In addition, the task scheduling of multi-core DSP needs to be controlled by the central processing unit. The application of the reconfigurable ASIC system still focuses on signal processing and underlying data. deal with

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