Resistive random access memory structure and manufacturing method thereof

Abstract

The invention provides a resistive random access memory structure and a manufacturing method thereof. The resistive random access memory structure includes a substrate, a plurality of memory cells, agap filling dielectric layer, a buffer layer, a first low dielectric constant dielectric layer and a first conductive plug, wherein the substrate is provided with an array region and a peripheral region; the plurality of memory cells and the gap filling dielectric layer covering the memory cells are located on the substrate and in the array region; the buffer layer is only located in the array region and covers the gap filling dielectric layer, and the material of the buffer layer is different from the material of the gap filling dielectric layer; the first low dielectric constant dielectric layer is only located in the peripheral region, and the material of the first low dielectric constant dielectric layer is different from the material of the buffer layer; a dielectric constant of the first low dielectric constant dielectric layer is less than 3; the top surface of the first low dielectric constant dielectric layer is coplanar with the top surface of the buffer layer; and the firstconductive plug penetrates through the buffer layer and the gap filling dielectric layer and is in contact with one of the memory cells.

Description

technical field [0001] The present invention relates to a memory device, and more particularly to a resistive random access memory structure and a manufacturing method thereof. Background technique [0002] Resistive random access memory (RRAM) has the advantages of simple structure, small area, low operating voltage, fast operating speed, long storage time, multi-state storage, and low power consumption. Therefore, the resistive random access memory has great potential to replace the current flash memory and become the mainstream of the next generation non-volatile memory. [0003] In known RRAMs, a chip usually includes an array area and a peripheral area. The array area includes a plurality of memory cells, and each memory cell includes a patterned bottom electrode layer, a resistive transition layer and a top electrode layer. The peripheral area is mainly logic circuits. In the peripheral area, in order to improve the operation speed of the logic circuit, the dielectr...

AI Technical Summary

Problems solved by technology

If the above-mentioned openings in the array area and the peripheral area are formed under the same conditions, the memory cells may be damaged due to excessive corrosion, thereby reducing the reliability and yield of the RRAM

On the other hand, if the above-mentioned openings in the array region and the peripheral region are formed in different etching steps, the complexity of the process, production cost and production time will be greatly increased.

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