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Heterogeneously integrated system-in-package structure and packaging method

A system-level packaging and packaging method technology, which is applied in the direction of semiconductor/solid-state device components, semiconductor devices, electrical components, etc., can solve the problem that the flatness of the tube and shell processing of the double-cavity structure is difficult to control, and the miniaturization and light weight cannot be achieved. Requirements, unfavorable production cost control and mass production, to achieve the effect of reducing development cost and cycle, reducing flatness risk, and solving packaging process problems

Pending Publication Date: 2021-01-22
北京轩宇空间科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] At present, in the case production of system-level packaging products, single-cavity structures are mostly used, but because the cavity size of the single-cavity structure is too large, it cannot meet the requirements of miniaturization and light weight, and there is a great risk of reliability ; There are also some existing technologies that use a double-cavity structure to improve reliability and integration. However, due to the difficulty in controlling the processing flatness of the shell with a double-cavity structure, the process requirements are relatively high, which is not conducive to production cost control and batch production. At the same time, the current dual-cavity structure is mostly used in the case of multi-chip integrated packaging, and rarely contains passive discrete devices; on the other hand, no matter the current dual-cavity structure, the stability in terms of structure is not Not ideal, as the requirements of the application environment are getting higher and higher, it cannot meet the requirements very well

Method used

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  • Heterogeneously integrated system-in-package structure and packaging method
  • Heterogeneously integrated system-in-package structure and packaging method
  • Heterogeneously integrated system-in-package structure and packaging method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0058] This example provides a heterogeneous integrated system-in-package structure, which includes two cavities.

[0059] Specifically, such as figure 1 As shown, the first cavity 4 is formed by digging a cavity on one side of the ceramic substrate 1 ; the second cavity 3 is formed by welding the Kovar ring 2 on the other side of the ceramic substrate 1 .

[0060] At the opening of the first cavity 4 , a first cover plate 41 for closing the first cavity 4 is assembled.

[0061] At the opening of the second cavity 3 , a second cover plate 31 for closing the second cavity 3 is assembled.

[0062] At least one chip 5 is respectively arranged in the first cavity 4 and the second cavity 3 , and the chip 5 is bonded to the surface of the ceramic substrate 1 through the conductive glue 7 .

[0063] At least one passive discrete component 6 is disposed in the first cavity 4 or the second cavity 3 , and the passive discrete component 6 is bonded to the surface of the ceramic substra...

Embodiment 2

[0089] This example provides a packaging method for a heterogeneously integrated system-in-package structure, which at least includes the following steps, and the flow of the steps is as follows: Figure 10 Shown:

[0090] Step 1) Shell Handling

[0091] A ceramic substrate 1 is provided, and a cavity is dug on one side to form a first cavity 4; a Kovar ring 2 is provided on the other side of the ceramic substrate 1 to form a second cavity 3, such as Figure 1~2 shown;

[0092] Among them, such as Figure 5~8 As shown, when the first cavity 4 is formed, a first reinforcing rib 42 integrally formed with the ceramic base 1 is formed at the same time, which is used to divide the first cavity 4 into two chambers; when the second cavity 3 is formed At the same time, a second rib 32 is welded on the surface of the ceramic base 1 of the second cavity 3, which is used to divide the second cavity 3 into two chambers; the first rib 42 and the second rib 32 are vertically arranged . ...

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Abstract

The invention provides a heterogeneous integrated system-in-package structure and a packaging method, and the structure comprises a ceramic substrate, wherein one side of which is dug to form a firstcavity; a Kovar ring which is arranged on the other surface of the ceramic substrate and is used for forming a second cavity; a first cover plate which is arranged at the opening of the first cavity and is used for sealing the first cavity; a second cover plate which is arranged at the opening of the second cavity and is used for sealing the second cavity, wherein at least one chip is arranged ineach of the first cavity and the second cavity, the chips are adhered to the surface of the ceramic substrate through a conductive adhesive, at least one passive discrete device is arranged in the first cavity or the second cavity, and the passive discrete device is adhered to the surface of the ceramic substrate through a conductive adhesive. A double-sided cavity structure is formed by adoptinga single-sided cavity-dug ceramic substrate and a Kovar ring, the structural stability is improved, the signal wiring is shortened, the interconnection efficiency and the system integration degree areimproved, the integration of active and passive devices is realized, the process maturity and the module reliability are both considered, and the guidance is provided for high-reliability SiP mass production.

Description

technical field [0001] The invention relates to the technical field of semiconductor packaging, in particular to a heterogeneously integrated system-level packaging structure and packaging method. Background technique [0002] System-in-Package SiP, System in Package technology is an integrated packaging form that mixes and loads components with different functions into the same package through different technologies, and thus provides system-level or subsystem-level functions. As a technical route to continue Moore's Law at the system level, SiP is an important means to meet the integration and miniaturization of aerospace electronic products. [0003] Due to the particularity of their application environments, aerospace electronics and military electronics need to be developed in terms of miniaturization, light weight, high density, and high reliability. SiP products in this field have advanced technology, mature technology, Product reliability is very important, interact...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/04H01L23/10H01L23/12H01L21/52H01L25/16
CPCH01L23/04H01L23/10H01L23/12H01L21/52H01L25/165H01L2224/48227H01L2924/19105
Inventor 刘鸿瑾李亚妮刘群张建锋
Owner 北京轩宇空间科技有限公司
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