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Metal oxide semiconductor field effect transistor, production method and application thereof

A technology of oxide semiconductor and field effect transistor, which is applied in the field of metal oxide semiconductor field effect transistor and its preparation, to achieve the effects of reducing resistance, improving single-pulse avalanche breakdown energy parameters, and reducing on-resistance

Active Publication Date: 2021-06-29
FOUNDER MICROELECTRONICS INT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But the working speed of this metal oxide semiconductor field effect transistor needs to be further improved

Method used

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  • Metal oxide semiconductor field effect transistor, production method and application thereof
  • Metal oxide semiconductor field effect transistor, production method and application thereof
  • Metal oxide semiconductor field effect transistor, production method and application thereof

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preparation example Construction

[0069] The present invention further provides a method for preparing the above metal oxide semiconductor field effect transistor, such as image 3 It includes the following steps S210-S216.

[0070] Step S210: sequentially forming a gate oxide material layer 102a and a polysilicon material layer on one side of the N-type base 101, removing the polysilicon material layer above the predetermined trench position and the predetermined second N+ region position to expose the gate oxide material layer 102a , forming a polysilicon layer 103 .

[0071] The growth temperature of the material of the gate oxide layer is 900°C-1200°C, specifically, but not limited to, 900°C, 1000°C, 1100°C or 1200°C.

[0072] The growth temperature of the above-mentioned polysilicon layer material is 500°C-800°C. Specifically, the growth temperature of the polysilicon layer material may be but not limited to 500°C, 600°C, 700°C or 800°C.

[0073] Understandably, a silicon nitride layer 104 may also be f...

Embodiment 1

[0104] This embodiment provides a metal oxide semiconductor field effect transistor, and the preparation method of the metal oxide semiconductor field effect transistor includes the following steps:

[0105] Step S210: Prepare a gate oxide layer 102 on the N-type substrate 101 containing an N-type substrate and an N-type epitaxial layer formed on the N-type substrate. The growth temperature of the material of the gate oxide layer 102 is 900° C. to 1200° C., and the thickness is 0.02 μm to 0.2 μm, and then prepare a polysilicon layer 103 on the gate oxide layer 102, the growth temperature of the polysilicon layer 103 is 500 ° C to 800 ° C, and the thickness is 0.3 μm to 1.5 μm, and then prepare a silicon nitride layer 104 on the polysilicon layer 103 , the growth temperature of the silicon nitride layer 104 is 600° C. to 1000° C., and the thickness is 0.1 μm to 1.0 μm; by dry etching, the polysilicon and the nitride layer above the predetermined second N+ region above the predet...

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Abstract

The invention discloses a metal oxide semiconductor field effect transistor, a production method and an application thereof. The metal oxide semiconductor field effect transistor comprises an N-type substrate, a groove is formed in one side of the N-type substrate, a P-body region, a P + region and an N + region are arranged in the N-type substrate, the P-body region wraps the groove, the P + region extends from the groove bottom of the groove to the P-body region, the N + region comprises a first N + region and a second N + region, the first N + region is arranged in the groove around the side wall of the groove and is exposed out of the P + region, and the second N + region is arranged between the adjacent P-body regions; a gate oxide layer is included and arranged on the side, provided with the groove, of the N-type substrate, and the groove is exposed out of the gate oxide layer; a polycrystalline silicon layer is included and is arranged on the gate oxide layer, and a contact hole is defined by the polycrystalline silicon layer, the gate oxide layer, the P + region and the N + region; and a first metal layer is included and arranged on the polycrystalline silicon layer and extends downwards to fill the contact hole. The transistor with the structure improves the working speed of a device while not reducing single-pulse avalanche breakdown energy.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a metal oxide semiconductor field effect transistor and its preparation method and application. Background technique [0002] Power integrated circuits refer to special integrated circuits that integrate power devices, low-voltage control circuits, signal processing and communication interface circuits into the same chip. The application of power integrated circuits not only reduces the size of the whole machine, reduces the connection, reduces the parasitic parameters, but also makes the cost lower, smaller and lighter, so it is widely used in communication and network, computer And consumer electronics, industrial and automotive electronics and many other fields. Power devices are the core part of power integrated circuits, occupying most of the chip area. Currently, power devices that are well compatible with integrated circuit technology are generally power me...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L29/16H01L21/336
CPCH01L29/1608H01L29/0684H01L29/0615H01L29/7827H01L29/7831H01L29/66068
Inventor 马万里
Owner FOUNDER MICROELECTRONICS INT
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