Time-to-digital converter for measuring decimal phase error of all-digital phase-locked loop

Abstract

The invention discloses a time-to-digital converter for measuring a decimal phase error of an all-digital phase-locked loop, which is based on a cascade structure of a buffer delay chain and a vernier delay chain, adopts a time window technology, delays a reference clock signal with lower frequency, and extracts a rising / falling edge of a single clock signal for signal detection; a circuit multiplexing technology is adopted, a rising / falling edge detection delay chain of the first-stage quantization unit is multiplexed, and meanwhile, a coarse quantization time error detection circuit and a two-stage resolution ratio scale factor detection circuit of the second-stage quantization unit are multiplexed; meanwhile, coarse quantization and fine quantization are carried out on the time deviation between the rising edge of the reference clock signal FREF and the nearest rising edge and falling edge of the feedback signal HCLK of the numerically controlled oscillator, so that a high-precision quantization result of the HCLK signal period is obtained. The measurement range is larger than 1.6 ns, the resolution ratio is higher than 2.8 ps, and the differential nonlinearity is smaller than 0.31 LSB.

Description

technical field [0001] The present invention relates to all-digital phase-locked loop technology, in particular to a time-to-digital converter for measuring the fractional phase error of the all-digital phase-locked loop, which can be used for the quantization of the phase error signal output by the phase detector in the all-digital phase-locked loop system, and belongs to field of digital integrated circuits. Background technique [0002] In recent years, with the continuous improvement of semiconductor technology, the feature size of MOS transistors has been continuously reduced, and the performance and power consumption of time domain and digital domain circuits have been continuously improved. Strong ability, short development cycle, low production cost, and easy transplantation have become an important direction for the development of phase-locked loop technology. The time-to-digital converter can convert the phase difference between the reference clock and the feedbac...

AI Technical Summary

Problems solved by technology

Nyquist time-to-digital converters often have a higher sampling rate, but the on-chip mismatch becomes more serious under advanced technology, which will deteriorate the resolution and linearity of the time-to-digital converter

Although the mismatch can be reduced by increasing the size of the MOS tube, it will increase power consumption and module area at the same time, and it goes against the trend of process evolution

The oversampling time-to-digital converter based on the ring oscillator can realize mismatch shaping, and has a large dynamic range and high resolution, but still has the disadvantages of complex structure, limited bandwidth and high power consumption. , and is affected by time skew errors caused by leakage currents and charge sharing, deteriorating its performance

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