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Semiconductor device and preparation method thereof

A semiconductor and device technology, applied in the field of semiconductor devices and their preparation, can solve the problems of easy lodging, decreased device performance and stability, large virtual line height and width, etc., to prevent lodging, improve performance and stability, and enhance strength. Effect

Active Publication Date: 2021-07-30
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a semiconductor device and its preparation method, which is used to solve the problem that the ratio of the height and width of the virtual line in the junction area is large, it is easy to fall, and then the performance and stability of the device are reduced.

Method used

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  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof
  • Semiconductor device and preparation method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0049] Figure 2k The top view of the semiconductor device provided for this embodiment, Figure 2j for Figure 2kSectional view along the aa direction and bb direction. The semiconductor device is, for example, a memory device such as a Dynamic Random Access Memory (DRAM) element, but not limited thereto.

[0050] like Figure 2k and Figure 2j As shown, the semiconductor device includes a substrate 100 , a plurality of word lines WL formed in the substrate 100 , and a plurality of bit lines BL and a plurality of dummy lines DL formed on the substrate 100 .

[0051] The substrate 100 is, for example, a silicon substrate, a silicon containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, and the like.

[0052] Wherein, the substrate 100 defines a memory cell region 100A (memory cell region), a peripheral circuit region (periphery region, not shown), and a boundary region 100C between the memory cell region 100A and the peripheral circuit reg...

Embodiment 2

[0109] image 3 The cross-sectional views of the semiconductor device provided in this embodiment along the directions aa and bb. like image 3 As shown, the difference from Embodiment 1 is that in this embodiment, the virtual line DL further includes a third insulating layer 208a, and the third insulating layer 208a is located between the first insulating layer 206a and the second insulating layer 206a. between layers 207a.

[0110] In this embodiment, the first insulating layer 206a, the second insulating layer 207a and the third insulating layer 208a all contain at least two or more insulating materials, for example, the first insulating layer 206a, the second insulating layer 207a and the third insulating layer 208a are composed of two or more materials among silicon oxide, silicon nitride, and silicon oxynitride, and the materials of the first insulating layer 206a and the third insulating layer 208a can be the same Or different, preferably, the material of the first ins...

Embodiment 3

[0116] Figure 5 The cross-sectional views of the semiconductor device provided in this embodiment along the directions aa and bb. like Figure 5 As shown, the difference from Embodiment 1 and Embodiment 2 is that in this embodiment, part of the thickness of the bottom of the first insulating layer 206a of the virtual line DL extends laterally to the first insulating layer of the adjacent virtual line DL. The bottom of the layer 206a is connected to cover part of the surface of the substrate 100 in the interface region 100C.

[0117] read on Figure 5 , in this embodiment, all the first insulating layers 206a of the virtual lines DL extend laterally to form a single film layer, so that at least part of the surface of the substrate 100 in the boundary region 100C is also covered by the The first insulating layer 206a is covered.

[0118] When the semiconductor device in this embodiment is prepared, it is similar to Embodiment 1. First, according to Figure 2a ~ Figure 2h s...

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Abstract

The invention provides a semiconductor device and a preparation method thereof. A substrate is provided with a storage unit region, a peripheral circuit region and a junction region located between the storage unit region and the peripheral circuit region; the plurality of bit lines are located on the substrate, are arranged at intervals in the first direction and extend into the junction area from the storage unit area in the second direction; the plurality of virtual lines are located on the substrate in the junction area, one virtual line is in butt joint with the end of one bit line and is aligned with the bit line in the second direction, and each virtual line comprises a first insulating layer and a second insulating layer which are sequentially stacked on the substrate. According to the invention, the transverse width of the bottom of the first insulating layer is larger than that of the top, the strength of the virtual line is enhanced by increasing the width of the bottom of the virtual line, the virtual line is prevented from lodging due to a bigger height-width ratio, and the performance and stability of the device are improved; moreover, since only the width of the bottom of the virtual line is increased, various parameters of the device are not affected.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background technique [0002] A memory, such as a dynamic random access memory (DRAM), generally has a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array. The memory has a plurality of word line structures and bit line structures, the word line structures are buried in the substrate, the bit line structures are formed on the substrate and electrically connected with corresponding memory cells, and the memory also includes a capacitor structure , the capacitance structure is used to store charges representing stored information, and the storage units can be electrically connected to the capacitance structure through a node contact structure, so as to realize the storage function of each storage unit. [0003] The memory also has a storage unit area and a peripheral ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L21/8242H10B12/00
CPCH10B12/34H10B12/48H10B12/09H10B12/482
Inventor 颜逸飞
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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