Memory operation condition checking method

Abstract

The invention relates to a memory operation condition checking method, which is implemented by a memory operation condition checking device, and can enable a central processing unit (CPU) on a mainboard to more accurately adjust correct supply voltage provided for each device under test (DUT) through voltage measurement values fed back by measurement units arranged at supply terminals of input voltages (VDD, VDDQ and VPP) of a plurality of device under test (DUT), therefore, the central processing unit can exert the highest efficiency, and the problem of voltage deviation of the memory power supply is solved by three operating voltages of VDD, VDDQ and VPP, so that correct supply voltage input to each to-be-tested memory module end can be accurately adjusted during mass production test, and consistency correction is achieved.

Description

technical field [0001] The present invention relates to a method for inspecting memory operating conditions, in particular to a method for solving the problem of memory power supply voltage deviation by using three operating voltages of VDD, VDDQ and VPP, and can more accurately adjust the correct supply for each memory module to be tested. Voltage, so that the central processing unit can exert the highest efficiency, especially refers to the method of accurately adjusting the correct supply voltage input to each memory module to be tested during mass production testing, so as to achieve consistent calibration. Background technique [0002] In a semiconductor device such as dynamic random access memory (DRAM), the memory die can be installed on a motherboard, and receive power supply from a central processing unit (CPU), and external The supplied power is delivered to a power management circuit (PMC), which manages power supplied to components of the memory system. Power ca...

AI Technical Summary

Problems solved by technology

However, the voltage of the power supply may deviate from the value set by the pulse width modulation (PWM) unit in the power management circuit due to the influence from program changes, load voltage at the end, etc.

[0003] In view of the fact that the power output from the power management circuit end, the path to the receiving end of the memory will produce unavoidable voltage deviation, so that the value actually reaching the memory end is unknown, and the prior art has not done this. Measurement, even if the PWM itself generates a feedback voltage, it can only know the set value just output, but the received value of the memory at the end has been affected, and it has been deviated by the load voltage at the end during operation, so Unable to correctly know the power consumption of each memory itself

[0004] According to the known technology, the voltage value output from the power management circuit to the input terminal of the memory is not measured to compensate for the lack of deviation of the power supply voltage. Therefore, it is generally impossible for the user to accurately adjust the correct value input to each memory terminal during actual use. Voltage values ​​required to achieve consistent calibration

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