Grid electrode and source electrode parallel connection adjustable resistance type super junction power device and manufacturing method thereof
A technology of power devices and manufacturing methods, which is applied in the field of gate-source parallel adjustable resistance super-junction power devices and their manufacturing, and can solve problems such as increased circuit design and manufacturing costs, reduced circuit versatility, and resistance failure. Achieve the effects of reducing cost expenditure, improving versatility, and increasing application range
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Embodiment 1
[0052] see figure 1 and figure 2 , in an embodiment of the present invention, a method for manufacturing a gate-source parallel adjustable resistance super-junction power device includes the following steps:
[0053] Step S1, chemical vapor deposition of an intrinsic epitaxial layer 2 on the surface of the silicon substrate 1; doping the intrinsic epitaxial layer 2 with pentavalent elements by ion implantation; the pentavalent elements include arsenic and phosphorus, in this implementation An example is specifically arsenic.
[0054] Step S2 , depositing a mask on the upper surface of the intrinsic epitaxial layer 2 , the composition of the mask is photoresist or a multilayer composite structure composed of photoresist and other insulator masks.
[0055] Step S3, defining the pattern of the columnar doped region 3 on the mask through a photolithography process; doping the intrinsic epitaxial layer 2 with trivalent element boron through ion implantation; and then removing th...
Embodiment 2
[0077] see figure 1 and figure 2 , in an embodiment of the present invention, a method for manufacturing a gate-source parallel adjustable resistance super-junction power device includes the following steps:
[0078] Step S1, chemical vapor deposition of an intrinsic epitaxial layer 2 on the surface of the silicon substrate 1; doping the intrinsic epitaxial layer 2 with pentavalent elements by ion implantation; the pentavalent elements include arsenic and phosphorus, in this implementation An example is specifically phosphorus element.
[0079] Step S2 , depositing a mask on the upper surface of the intrinsic epitaxial layer 2 , the composition of the mask is photoresist or a multilayer composite structure composed of photoresist and other insulator masks.
[0080] Step S3, defining the pattern of the columnar doped region 3 on the mask through a photolithography process; doping the intrinsic epitaxial layer 2 with trivalent element boron through ion implantation; and then ...
Embodiment 3
[0102] see figure 1 and figure 2 , in an embodiment of the present invention, a method for manufacturing a gate-source parallel adjustable resistance super-junction power device includes the following steps:
[0103] Step S1, chemical vapor deposition of an intrinsic epitaxial layer 2 on the surface of the silicon substrate 1; doping the intrinsic epitaxial layer 2 with a trivalent element by ion implantation; the trivalent element includes boron, specifically in this embodiment for the boron element.
[0104] Step S2 , depositing a mask on the upper surface of the intrinsic epitaxial layer 2 , the composition of the mask is photoresist or a multilayer composite structure composed of photoresist and other insulator masks.
[0105] Step S3, defining the pattern of the columnar doped region 3 on the mask through a photolithography process; doping the intrinsic epitaxial layer 2 with pentavalent elements through ion implantation, the pentavalent elements including arsenic and ...
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Abstract
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