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Anti-EMI super-junction VDMOS device and preparation method thereof

A device and conductive type technology, applied in the field of anti-EMI superjunction VDMOS devices and preparation, can solve the problems of electromagnetic pollution of components and equipment, parasitic transistor turn-on, fast switching speed, etc., to reduce EMI electromagnetic radiation noise, reduce switching The effect of shock and endurance improvement

Pending Publication Date: 2022-02-25
济南市半导体元件实验所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the total amount of doping of the P-column and N-column of the super-junction MOSFET needs to be the same or equivalent. If the mismatch between the two is serious, the withstand voltage will be greatly reduced, which poses a challenge to the processing technology.
In addition, due to the mutual depletion of the N-column and the P-column of the super-junction MOSFET, the switching speed is fast, and the voltage oscillation dV / dt and the current oscillation dI / dt between the drain and the source will be faced during the switching process. On the one hand, High voltage oscillation dV / dt is superimposed on the device, which can easily cause parasitic transistors to turn on, resulting in device failure; Devices and equipment produce serious electromagnetic pollution

Method used

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  • Anti-EMI super-junction VDMOS device and preparation method thereof

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Experimental program
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Effect test

Embodiment 1

[0053] like figure 1 As shown, Embodiment 1 of the present invention provides a kind of anti-EMI super junction VDMOS device, comprising:

[0054] Drain Metal 1;

[0055] a substrate 2 of the first conductivity type located above the drain metal 1;

[0056] A super junction drift region located above the substrate 2 of the first conductivity type, the super junction drift region includes a drift region 3 of the first conductivity type and a drift region 4 of the second conductivity type;

[0057] The second conductivity type base region 5 located on the upper part of the superjunction drift region;

[0058] The second conductivity type ohmic contact region 6 and the first conductivity type source region 7 located inside the second conductivity type base region 5;

[0059] a gate oxide layer 10 located above the base region 5 of the second conductivity type;

[0060] a gate 11 located above the gate oxide layer 10;

[0061] The source metal 8 located above the second condu...

Embodiment 2

[0069] Embodiment 2 of the present invention provides a method for preparing an anti-EMI super junction VDMOS device, including the following process:

[0070] Take the semiconductor substrate material of the first conductivity type;

[0071] Epitaxially form the drift region of the super junction structure on the substrate material;

[0072] Etching a trench in the super junction drift region, the trench runs through the entire super junction drift region to the first conductivity type substrate;

[0073] growing an oxide layer dielectric on the sidewall of the trench;

[0074] Depositing and forming a U-shaped semi-insulating polysilicon layer in the trench;

[0075] Depositing an oxide layer dielectric in the U-shaped semi-insulating polysilicon layer;

[0076] growing a gate oxide over the drift region;

[0077] Depositing a polysilicon gate over the gate oxide;

[0078] Ion implantation in the upper part of the drift region and push the junction to form the base regi...

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Abstract

The invention provides an anti-EMI super-junction VDMOS device and a preparation method thereof. The device is provided with a composite dielectric layer consisting of an oxide layer (SiO2), a semi-insulating polycrystalline silicon layer (SIPOS) and an oxide layer (SiO2) in a super-junction drift region, wherein the oxide layer isolates a drift region from the SIPOS layer, the lower portion of the SIPOS layer is connected with the device drain electrode metal, and the upper portion of the SIPOS layer is connected with the device source electrode metal. When the device is in a turn-off state, the composite dielectric layer assists in depletion of the super junction drift region, so that the doping concentration of the drift region can be greatly improved, and the phenomenon that the withstand voltage is reduced due to mismatch between a super junction P column and an N column can be relieved; and in the switching process of the device, because the SIPOS is directly connected with the source electrode and the drain electrode of the device, the output capacitance Coss of the device is greatly improved, the switching oscillation is reduced, and thus the voltage oscillation dV / dt failure possibility and the EMI noise of the device are reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an anti-EMI super junction VDMOS device and a preparation method. Background technique [0002] The statements in this section merely provide background art related to the present invention and do not necessarily constitute prior art. [0003] Super-junction MOSFET devices are widely used in various fields such as switching power supplies, automotive electronics, and motor drives. It uses the charge compensation theory, and the drift region is composed of a series of alternating highly doped P columns and N columns, and uses the lateral electric field of the P columns and N columns to deplete each other, thereby increasing the concentration of the drift region and reducing the on-resistance. [0004] However, the total amount of doping of the P-pillar and the N-pillar of the super-junction MOSFET needs to be the same or equal. If the mismatch between the two is ser...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/40H01L23/552H01L21/336
CPCH01L29/7813H01L29/407H01L23/552H01L29/66734
Inventor 孙德福李东华李泽宏
Owner 济南市半导体元件实验所
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