33results about How to "Increase the output capacitance" patented technology

A semiconductor device includes a semiconductor substrate having a conductive type, a source metal layer, a gate metal layer, at least one transistor device, a heavily doped region having the conductive type, a capacitor dielectric layer, a conductive layer. The source metal layer and the gate metal layer are disposed on the semiconductor substrate. The transistor device is disposed in the semiconductor substrate under the source metal layer. The heavily doped region, the capacitor dielectric layer and the conductive layer constitute a capacitor structure, disposed under the gate metal layer, and the capacitor structure is electrically connected between a source and a drain of the transistor device.

A semiconductor device having a novel structure is provided. Fluctuation in the grayscale voltage due to an offset voltage is suppressed. When a current corresponding to a lower-bit grayscale voltage is generated in a transconductance amplifier, voltages V_HI and V_LO supplied to the transconductance amplifier are alternately input to two input terminals in accordance with a digital signal of the most significant bit of lower bits. Since a change corresponding to the offset voltage is added to both the maximum and minimum values of the current output from the transconductance amplifier, fluctuation in the grayscale voltage due to the offset voltage can be suppressed.

A laterally diffused metal-oxide-semiconductor device includes a substrate, a gate dielectric layer, a gate polysilicon layer, a source region, a drain region, a body region, a first drain contact plug, a source polysilicon layer, an insulating layer, and a source metal layer. The source polysilicon layer disposed on the gate dielectric layer above the drain region can serve as a field plate to enhance the breakdown voltage and to increase the drain-to-source capacitance. In addition, the first drain contact plug of the present invention can reduce the drain-to-source on-resistance and the horizontal extension length.

The invention relates to a synchronous resonance-based high-sensitivity voltage, resistance and capacitance superposition force sensor and belongs to the field of synchronous resonance cantilever force sensors capable of realizing voltage, resistance and capacitance superposition. The lower part of a C-shaped supporting structure is fixedly connected with a piezoelectric excitation structure; the middle part of the C-shaped supporting structure is connected with a U-shaped beam, a T-shaped beam and a synchronous coupling beam; two sides of the T-shaped beam is connected with the synchronous coupling beam; the inner side of the U-shaped beam is connected with the synchronous coupling beam; a plurality of piezoelectric vibration pick-up structures are deposited on the surface of the T-shaped beam; the surface of the fixed end of the T-shaped beam is provided with a piezoresistance vibration pick-up structure; and two capacitance vibration pick-up structures form a differential capacitance vibration pick-up structure. The force sensor of the invention is novel in structure. Based on simple structure design, the piezoelectric, piezoresistance and capacitance vibration pick-up structures are integrated in the same structure, the output signals of the three structures are superposed, and therefore, output voltage can be further amplified, and the detection sensitivity of the sensor can be improved.

A sense circuit includes a differential amplifier circuit including an inverting input section, a non-inverting input section and an output section, an electrical capacitor connected between the inverting input section and the output section, and a field effect transistor including a source, a drain, and a gate. One of the source and the drain is connected to the inverting input section, and the other of the source and the drain is connected to the output section. A reference potential is supplied to the non-inverting input section, and an output section of a photoelectric conversion cell having an added switching function is connected to the inverting input section.

A high voltage semiconductor device is provided and includes an n⁻-type region encompassed by a p⁻ well region and is provided on a p⁻-type silicon substrate. A drain n⁺-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n⁺-region. A source n⁺-region is formed in the p base region. Further, a p⁻-region is provided that passes through the n⁻-type region to the silicon substrate. The n⁻-type region is divided, by the p⁻-region, into a drift n⁻-type region having the drain n⁺-region and a floating n⁻-type region having a floating electric potential.

A grayscale voltage generator circuit that is less likely to be influenced by the offset voltage is provided. The grayscale voltage generator circuit is a semiconductor device that includes a D/A converter circuit, a first G_m amplifier, a second G_m amplifier, a current control circuit, an output buffer, and a selector circuit. The D/A converter circuit generates a first voltage and a second voltage from an upper bit of a digital signal. The current control circuit generates a first current from a lower bit of the digital signal and functions as a current source of the first G_m amplifier. The output buffer generates a third voltage from currents output from the first G_m amplifier and the second G_m amplifier. The third voltage is input to the second G_m amplifier. The selector circuit selects voltages that are to be input to the first G_m amplifier and the second G_m amplifier.

A semiconductor device with a novel structure. An upper-bit grayscale voltage and a lower-bit grayscale voltage are separately produced, and then the grayscale voltages are converted into currents and the currents are synthesized. The obtained current is converted into a voltage, and thus an intended grayscale voltage is obtained. The upper-bit grayscale voltage and the lower-bit grayscale voltage are generated using respective D/A converter circuits each including a resistor string circuit and a pass transistor logic. The increase in the number of transistors supplied with high voltage, which occurs along with the increase in the number of digital signal bits, is prevented. Thus, the increase in parasitic capacitance can be suppressed, and a smaller circuit area and higher response speed are obtained.

There is provided an output driver for use in a semiconductor device capable of remarkably improving linearity of impedance by reducing or minimizing a change of an impedance for output data caused due to a change of an external power supply. The output driver for outputting internal data of a semiconductor device to the exterior of a chip comprises a first driving section including a driving transistor to maintain an impedance for applied data at a certain level in response to the data; and a second driving section for compensating for linearity of the impedance in response to an operation signal from the driving transistor of the first driving section and providing an output terminal with the data.

The invention relates to a piezoelectric transformer comprising a piezoelectric element (1) of length L, wherein an input voltage Uin can be applied at an input side (2) for transformation into an output voltage Uout at an output side (3) according to a transformation ratio formula (I). The piezoelectric element (1) has multiple plies (4a, 4b, 4c) of inner electrodes, which are arranged in multiple different layers (S1, S2, S3). Each ply (4a, 4b, 4c) of inner electrodes extends along at least one predetermined sub-section of a predetermined length, wherein sub-sections of plies (4a, 4c) of a first group of layers (S1, S3) and sub-sections of plies (4b) of a second group of layers (S2) have different dimensions, such that the piezoelectric transformer satisfies the following condition: Cin<=N2Cout, wherein Cin represents the input capacity, Cout represents the output capacity and N represents the transformation ratio of the ideal transformer.

The invention discloses a shield gate trench metal oxide semiconductor field effect transistor (MOSFET). The structure comprises a primitive cell region and a peripheral region, a device unit structure of a shield gate trench MOSFET is formed in the primitive cell region, a trench MOS capacitor used for reducing nonlinearity of output capacitance of the shield gate trench MOSFET is formed in the peripheral region, and the trench MOS capacitor comprises a second gate structure which is formed in a second trench and comprises a second polycrystalline silicon shield field plate, wherein the second trench is formed in a first epitaxial layer doped with the first conductivity type, and a second shielding dielectric layer is isolated between the second polycrystalline silicon shielding field plate and the first epitaxial layer, the source region is not formed on the surface of the first epitaxial layer covered on the side surface of the second trench, and the first epitaxial layer on the side surface of the second trench and the first epitaxial layer of the primitive cell region form the drift region of the whole device; the drain region of the whole device is formed at the bottom of thefirst epitaxial layer; and the top of the second polycrystalline silicon shielding field plate is connected to the source electrode through a contact hole. According to the invention, the minimum value of the output capacitance can be improved, and the nonlinearity of the output capacitance is improved.

The invention discloses a trench metal oxide semiconductor field effect transistor (MOSFET). The structure comprises a primitive cell region and a peripheral region, wherein a device unit structure ofa trench MOSFET is formed in the primitive cell region, a trench MOS capacitor used for reducing the nonlinearity of the output capacitance of the trench MOSFET is formed in the peripheral region, and the trench MOS capacitor comprises a second trench gate formed by superposing a second gate dielectric layer and a second polysilicon gate which are formed in a second trench; a source region is notformed on the surface of the first epitaxial layer covered on the side surface of the second polysilicon gate, a drift region formed by the first epitaxial layer extends into the whole primitive cellregion and the peripheral region, and a drain region is formed on the back surface of the drift region; the top of the second polysilicon gate is connected to the source electrode through a contact hole; the trench MOS capacitor and the device unit structure form a parallel structure, and the output capacitance of the whole trench MOSFET is improved and the nonlinearity of the output capacitanceis reduced when the device is reversely biased. The invention further discloses a manufacturing method of the trench MOSFET.

The invention provides an anti-EMI super-junction VDMOS device and a preparation method thereof. The device is provided with a composite dielectric layer consisting of an oxide layer (SiO2), a semi-insulating polycrystalline silicon layer (SIPOS) and an oxide layer (SiO2) in a super-junction drift region, wherein the oxide layer isolates a drift region from the SIPOS layer, the lower portion of the SIPOS layer is connected with the device drain electrode metal, and the upper portion of the SIPOS layer is connected with the device source electrode metal. When the device is in a turn-off state, the composite dielectric layer assists in depletion of the super junction drift region, so that the doping concentration of the drift region can be greatly improved, and the phenomenon that the withstand voltage is reduced due to mismatch between a super junction P column and an N column can be relieved; and in the switching process of the device, because the SIPOS is directly connected with the source electrode and the drain electrode of the device, the output capacitance Coss of the device is greatly improved, the switching oscillation is reduced, and thus the voltage oscillation dV/dt failure possibility and the EMI noise of the device are reduced.

A comparing device includes a first stage comparator and a second stage comparator serially coupled to the first stage comparator, wherein output lines of the second stage comparator are disposed to be overlapped with respective input lines of the second stage comparator.