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Silicon-based broadband high-speed reconfigurable orthogonal frequency divider

An orthogonal frequency divider and broadband technology, which is applied in the field of silicon-based broadband high-speed reconfigurable orthogonal frequency divider, can solve the problems of increasing bias current, increasing power consumption, and affecting the highest operating frequency, etc., so as to reduce power consumption Effect

Pending Publication Date: 2022-05-27
10TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If the resistance value is too large, the RC time constant will increase, and the corresponding charge and discharge time will increase, thus affecting the highest operating frequency; increase; this contradictory relationship makes the traditional static load structure often cannot have a larger maximum operating frequency
2) Dynamic resistive load
However, this structure has the disadvantage of a narrow frequency division range, which makes it difficult to meet the needs of millimeter-wave broadband applications and even full-band multi-communication protocol applications.

Method used

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  • Silicon-based broadband high-speed reconfigurable orthogonal frequency divider
  • Silicon-based broadband high-speed reconfigurable orthogonal frequency divider
  • Silicon-based broadband high-speed reconfigurable orthogonal frequency divider

Examples

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Embodiment Construction

[0017] see figure 1 . In an illustrative preferred embodiment described below, a silicon-based broadband high-speed reconfigurable quadrature divider includes: a master-slave two differential latches LATCH1 and LATCH2 with a tail current bias array, a load clock A feedforward radio frequency switch unit and a differential output buffer Buffer connected to I / Q channels respectively, wherein the data signal differential output terminals Q and QB of the main differential latch LATCH1 are sequentially connected to the data signal differential input of the slave differential latch LATCH2 Terminals D and DB; the data signal output terminals Q and QB of the differential latch LATCH2 are connected to the buffer Buffer1, and the data signal output terminals Q and QB of the LATCH1 are connected to another buffer Buffer2; the load clock feedforward RF switch unit outputs the differential output of the clock signal Ports Z0 and Z1 are connected to the clock feed port CLK of the master a...

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PUM

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Abstract

The silicon-based broadband high-speed reconfigurable orthogonal frequency divider disclosed by the invention is wide in frequency division range, high in working frequency and low in power consumption. According to the technical scheme, an external differential clock signal is transmitted to clock signal differential input ports of a master differential latch and a slave differential latch through a capacitor, and is transmitted to a clock signal differential input port of a load clock feed-forward radio frequency switch unit through a capacitor 4; the two differential latches sample an input signal, a clock input differential signal passes through a capacitor, a sine wave or square wave clock signal is transmitted to the load clock feed-forward radio frequency switch unit, and the clock frequency is controlled; when the input clock frequency is low, the switch is switched on, the master differential latch 1 works in a dynamic state, when the differential normal phase clock signal input port of the differential latch is at a high level, the switch is switched off, the slave differential latch 2 works in a static state, and buffers of the output ends of the master and slave differential latches directly drive a post-stage circuit.

Description

technical field [0001] The invention belongs to the technical field of radio frequency wireless transceiver front-end integrated circuits, and in particular relates to a broadband high-speed reconfigurable quadrature frequency divider based on a silicon-based process with an operating frequency covering a low frequency (~MHz) to a millimeter wave (~30GHz) frequency band, in particular The invention relates to a load clock feedforward CMOS broadband high-speed dynamic current mode logic DCML (Dynamic Currentmode Logic) frequency divider structure with switch adjustment, which is mainly used in a millimeter wave wireless transceiver front-end system. Background technique [0002] The continuous development of silicon-based millimeter-wave technology has brought rapid changes to people's lives, and various communication standard protocols and technical applications have emerged one after another. Among them, the wireless transceiver front-end system not only needs to meet more ...

Claims

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Application Information

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IPC IPC(8): H03K23/66
CPCH03K23/66Y02D30/70
Inventor 刘智卿王友华张然李航标赵晓冬姚明张凯
Owner 10TH RES INST OF CETC
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