Semiconductor structure and manufacturing method thereof
A manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve the problems of poor electrical performance of DRAM and low reliability of DRAM operation.
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment 1
[0058] The method for fabricating a semiconductor structure provided by the embodiments of the present application is used for fabricating a semiconductor structure, and the semiconductor structure includes but is not limited to a DRAM.
[0059] figure 1 A schematic flowchart of a method for fabricating a semiconductor structure provided in an embodiment of the present application; figure 2 A schematic top view of a substrate provided with bit lines and word lines provided in an embodiment of the present application; Figure 3 to Figure 16 It is a schematic cross-sectional structure diagram of the formation process of the semiconductor structure provided by the embodiment of the present application.
[0060] like figure 1 As shown, the method for fabricating a semiconductor structure provided by the embodiment of the present application includes the following steps:
[0061] Step S101 : providing a substrate in which a plurality of active regions are arranged at intervals....
Embodiment 2
[0125] The semiconductor structure 100 provided in the embodiment of the present application is fabricated by using the fabrication method of the semiconductor structure 100 in the first embodiment.
[0126] refer to Figure 2 to Figure 17 As shown, the semiconductor structure 100 includes a substrate 10 on which a shallow trench isolation structure is formed, and the shallow trench isolation structure isolates a plurality of regions, and the plurality of regions form a plurality of active regions 101 ( like figure 2 shown). The substrate 10 is further provided with a groove 103 and an isolation structure 104 for isolating the groove 103 (eg Figure 4 shown), at least the active region 101 is exposed in the groove 103, and the bit line contact structure 111 is provided on the groove 103. It can be understood that the bit line contact structure 111 in the groove 103 and the one in the groove 103 have The active regions 101 are in one-to-one correspondence and contact, so th...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 


