Method for forming semiconductor element with recess type source electrode/drain electrode contact surface
A semiconductor and drain technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of inability to overcome excessive source/drain load, increase in source/drain resistance, increase in resistance, etc. problems, to avoid short channel effects, avoid junction leakage, and improve reliability.
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Embodiment 1
[0034] 2A to 2G , which is a schematic cross-sectional view of the process of forming a semiconductor device with recessed source / drain junctions according to a preferred embodiment of the present invention.
[0035] Please refer to Figure 2A First, a thin oxide layer 202 , a conductive layer 204 and a dielectric layer 206 are formed on a substrate 200 . The material of the conductive layer 204 is, for example, polysilicon or other materials suitable for the gate conductive layer, and the material of the dielectric layer 206 is, for example, TEOS.
[0036] After that, please refer to Figure 2B , pattern the dielectric layer 206, the conductive layer 204 and the thin oxide layer 202 by a lithography etching process to form a cap layer 206a, a gate conductive layer 204a and a gate oxide layer 202a to form a gate structure .
[0037] Then, please refer to Figure 2C , a spacer 208 is formed on the sidewall of the gate structure. The spacer 208 is formed by a low pressure...
Embodiment 2
[0045] 3A to 3D , which is a schematic cross-sectional view of the process of forming a semiconductor device with recessed source / drain junctions according to another preferred embodiment of the present invention.
[0046] Please refer to Figure 3A First, a thin oxide layer 202 and a conductive layer 204 are formed on a substrate 200 . The material of the conductive layer 204 is, for example, polysilicon or other materials suitable for the gate conductive layer, and the material of the dielectric layer 206 is, for example, TEOS-silicon oxide.
[0047] After that, please refer to Figure 3B , using a lithography etching process to pattern the conductive layer 204 and the thin oxide layer 202 to form a gate conductive layer 204a and a gate oxide layer 202a to form a gate structure. Then, a spacer 208 is formed on the sidewall of the gate structure. The material of the spacer 208 is, for example, silicon nitride or silicon oxide. The method of forming the spacer 208 is the...
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