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Method for forming semiconductor element with recess type source electrode/drain electrode contact surface

A semiconductor and drain technology, used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem of inability to overcome excessive source/drain load, increase in source/drain resistance, increase in resistance, etc. problems, to avoid short channel effects, avoid junction leakage, and improve reliability.

Inactive Publication Date: 2006-02-15
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the shrinkage of the source / drain size will cause its resistance to rise, making the current of the component smaller and resulting in an excessive load (Over Loading)
If the source / drain junction depth (JunctionDepth) is increased to solve the problem of source / drain resistance increase, not only will the short channel effect (Short Channel Effect) be derived, but also the junction leakage (Junction Leakage) and other issues
If high-concentration doping is used to make the source / drain of the shallow junction to avoid problems such as short channel effects and junction leakage caused by too deep junctions, then due to the limitation of solid solubility, and cannot overcome the problem of excessive source / drain loading
In addition, in the known method, there is also a method of reducing the spacer and forming the source / drain of the shallow junction to solve the short channel effect, but this method is easy to make the source / drain of the shallow junction The metal silicide layer produces unacceptable junction leakage

Method used

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  • Method for forming semiconductor element with recess type source electrode/drain electrode contact surface
  • Method for forming semiconductor element with recess type source electrode/drain electrode contact surface
  • Method for forming semiconductor element with recess type source electrode/drain electrode contact surface

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Embodiment 1

[0034] 2A to 2G , which is a schematic cross-sectional view of the process of forming a semiconductor device with recessed source / drain junctions according to a preferred embodiment of the present invention.

[0035] Please refer to Figure 2A First, a thin oxide layer 202 , a conductive layer 204 and a dielectric layer 206 are formed on a substrate 200 . The material of the conductive layer 204 is, for example, polysilicon or other materials suitable for the gate conductive layer, and the material of the dielectric layer 206 is, for example, TEOS.

[0036] After that, please refer to Figure 2B , pattern the dielectric layer 206, the conductive layer 204 and the thin oxide layer 202 by a lithography etching process to form a cap layer 206a, a gate conductive layer 204a and a gate oxide layer 202a to form a gate structure .

[0037] Then, please refer to Figure 2C , a spacer 208 is formed on the sidewall of the gate structure. The spacer 208 is formed by a low pressure...

Embodiment 2

[0045] 3A to 3D , which is a schematic cross-sectional view of the process of forming a semiconductor device with recessed source / drain junctions according to another preferred embodiment of the present invention.

[0046] Please refer to Figure 3A First, a thin oxide layer 202 and a conductive layer 204 are formed on a substrate 200 . The material of the conductive layer 204 is, for example, polysilicon or other materials suitable for the gate conductive layer, and the material of the dielectric layer 206 is, for example, TEOS-silicon oxide.

[0047] After that, please refer to Figure 3B , using a lithography etching process to pattern the conductive layer 204 and the thin oxide layer 202 to form a gate conductive layer 204a and a gate oxide layer 202a to form a gate structure. Then, a spacer 208 is formed on the sidewall of the gate structure. The material of the spacer 208 is, for example, silicon nitride or silicon oxide. The method of forming the spacer 208 is the...

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Abstract

First, a substrate is provided. next, a grid structure is formed on the substrate. A top cap layer is formed on the top part in the grid structure. Then, a gap wall is formed on the sidewall of the grid structure. An opening is formed on the substrate positioned at two sides of the gap wall by using the top cap layer and the gap wall as the etching mask. Finally, a selectivity film is formed in the opening as a source pole / drain pole.

Description

technical field [0001] The present invention relates to a method for manufacturing a semiconductor element, and more particularly, to a method for forming a semiconductor element with recessed source / drain junctions. Background technique [0002] In addition to a gate oxide layer and a gate structure, a metal oxide semiconductor device (MOS) also includes a semiconductor region with electrical properties opposite to that of the silicon substrate in the substrate on both sides of the gate structure, which is called source / drain. In the field of very large scale integration (VLSI), metal oxide semiconductor components are widely used, such as logic circuits and memory components, etc., metal oxide semiconductor components are an indispensable semiconductor component. [0003] 1A to 1C As shown, it is a cross-sectional schematic diagram of a known manufacturing process of a semiconductor device. [0004] Please refer to Figure 1A First, a substrate 100 is provided, and then...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/285H01L21/336
Inventor 张国华黄文信
Owner MACRONIX INT CO LTD