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Method for producing nano-transistor with high performance

A technology of transistors and nanotubes, applied in the field of high-performance nanotransistor preparation, can solve the problems of single carbon nanotubes, large leakage current of transistors, difficult sorting and positioning, etc., so as to improve life, reduce leakage current, improve quality effect

Inactive Publication Date: 2006-08-09
INST OF PHYSICS - CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the preparation of this kind of transistor, it is difficult to ensure that a single carbon nanotube is selected, and there are also problems of difficult sequencing and positioning.
If multiple carbon nanotubes are in contact with the metal electrodes of the source and drain, the fabricated transistor will have large leakage current and small transconductance.

Method used

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  • Method for producing nano-transistor with high performance
  • Method for producing nano-transistor with high performance
  • Method for producing nano-transistor with high performance

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] Choose n in (001) orientation + Type highly doped silicon, a layer of 500nm thick SiO is grown on the silicon surface by thermal oxidation 2 Layer, as the insulating layer 2, thereby completing the preparation of the substrate 1, wherein the highly doped substrate is used as the back gate. Coating, exposure, development and fixing on the surface of the substrate 1, 10nm-thick titanium and 50nm-thick gold are successively deposited by electron beam evaporation method, and the source electrode 3 and the drain electrode 4 are formed after stripping and cleaning. The size of each electrode is 100μm×100μm, the electrode spacing is 1μm; a single carbon nanotube is placed on the source and drain electrodes by atomic force microscope technology and forms good electrical contact with the two electrodes respectively. The carbon nanotube is synthesized by chemical vapor deposition method with a diameter of 15nm . figure 1 A schematic diagram of its structure.

[0054] Place the...

Embodiment 2

[0058] Choose n of (111) orientation + Type highly doped silicon, deposit 5μm thick SiO on the silicon surface 2 Layer, as the insulating layer 2, completes the preparation of the substrate 1, where the highly doped substrate acts as the back gate. Coating, exposure, development and fixing on the surface of the substrate 1, using the thermal evaporation method to deposit gold with a thickness of 800nm, after stripping, the source electrode 3 and the drain electrode 4 are formed. The size of each electrode is 50μm×50μm, and the electrode spacing is 3 μm; a single single-walled carbon nanotube is placed on two electrodes and forms good electrical contact with the two electrodes respectively, wherein the carbon nanotube is a single-walled carbon nanotube synthesized by a chemical vapor deposition method. Its structural diagram refers to figure 1 .

[0059] Place the above-prepared carbon nanotube device in a vacuum chamber with a vacuum degree of 1×10 -6 mbar, the temperature...

Embodiment 3

[0061] Choose n of (111) orientation + Type highly doped silicon, deposited 3nm thick ZrO on the silicon surface 2 , as the insulating layer 2 of the substrate, where the highly doped substrate acts as the back gate. Cover the surface of the substrate insulating layer with 50nm thick PMMA, and bake at 100°C for 1 hour; place the selected single multi-walled carbon nanotube on the PMMA covered on the surface of the substrate insulating layer, and then cover it with a thickness of 50nm PMMA, bake at 100 °C for 1 hr. Electron beam lithography is used to prepare source-drain electrode patterns at both ends of carbon nanotubes, and 80nm-thick aluminum is deposited by electron beam deposition. After stripping and cleaning, source electrodes 3 and drain electrodes 4 are formed. The size of each electrode is 100μm× 100μm, electrode spacing is 1μm; figure 2 A schematic diagram of its structure.

[0062] Using the method described in Example 1, a scanning bias voltage was applied a...

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Abstract

The preparation method of high-performance nano transistor includes the following steps: on the conductive wafer making oxidation, growth or deposition of insulating layer to prepare the required substrate; on the substrate preparing metal electrodes of source and drain; placing nano material between two electrodes and making its two ends be respectively connected with two electrodes to form good ohmic contact; placing the above-mentioned device in vacuum chamber and galvanizing two ends of nano material, after the galvanization is stopped, making lead and packaging so as to obtain the invented high-performance nano transistor.

Description

technical field [0001] The invention relates to the preparation of microelectronic devices and the improvement of their performance, in particular to a preparation method of high-performance nanometer transistors. Background technique [0002] With the continuous development of microelectronics technology, the size of devices is getting smaller and smaller, and the integration level is getting higher and higher. When chips made of silicon cannot be made smaller, carbon nanotubes are likely to be the best choice to replace silicon. In terms of computer miniaturization and energy-saving research, the scientific and technological progress caused by carbon nanotubes will exceed people's imagination. When the gate length of silicon field-effect transistors is reduced to a critical dimension of 35 nanometers, its price will no longer decrease with the reduction in size. It is predicted that in the next 10 to 15 years, it will be difficult for silicon-made chips to become smaller...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/328H01L21/334
Inventor 李秋红王太宏
Owner INST OF PHYSICS - CHINESE ACAD OF SCI