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Structure of non-volatile memory and producing method thereof

A non-volatile, manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as difficult improvement, time-consuming photomask production, and insufficient current of embedded bit lines, etc., to achieve reduction The effect of production costs

Inactive Publication Date: 2004-07-07
MACRONIX INT CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this method must design a mask with a special pattern
Therefore, in addition to the time-consuming production of the photomask, it also increases the difficulty and cost of manufacturing the photomask.
In addition, it is extremely difficult to improve (debug) the defects of the mask pattern after the mask is manufactured.
[0005] In addition, in the known method, if the code mask used in the code implantation process has the problem of misalignment or critical dimension deviation, the code ions originally planned to be implanted in the channel region will also diffuse to the implanted channel area. bit line
In this way, the ion concentration in the buried bit line will change, and the current of the buried bit line will be insufficient.

Method used

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  • Structure of non-volatile memory and producing method thereof
  • Structure of non-volatile memory and producing method thereof
  • Structure of non-volatile memory and producing method thereof

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Embodiment Construction

[0025] Figure 1A to Figure 1F As shown, it is a cross-sectional schematic view of the manufacturing process of the mask ROM according to a preferred embodiment of the present invention.

[0026] Please refer to Figure 1A , first form a strip-shaped dielectric layer 102 on a substrate 100, wherein the substrate 100 is, for example, a P-type silicon substrate, and the strip-shaped dielectric layer 102 is, for example, a strip-shaped silicon oxide layer, a strip-shaped nitride The silicon layer or a strip-shaped silicon oxynitride layer, and the method of forming the strip-shaped dielectric layer 102 is, for example, depositing a dielectric layer (not shown) on the substrate 100 by chemical vapor deposition, and then using a The dielectric layer is patterned by a photolithographic etching process to form strip-shaped dielectric layers 102 .

[0027] Next, an ion implantation step is performed using the strip-shaped dielectric layer 102 as an implantation mask to form a buried ...

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Abstract

A manufacturing method for non-volatile memory, first forms a strip dielectric layer on a base, and forms a flush type bit line in the base at the both sides of the dielectric layer. Then patternize the strip dielectric layer, to form several massive dielectric layer, afterwards forms a coding mask layer, expose part of massive dielectric layer. Then takes coding mask layer as a etching mask, detaches the exposure part of the strip massive dielectric layer. After detaching the coding mask layer, form a gate dielectric layer, further form a word ling on the base.

Description

technical field [0001] The present invention relates to a structure of a non-volatile memory and its manufacturing method, and in particular to a mask ROM (Mask ROM) structure and its manufacturing method. Background technique [0002] The structure of a general mask ROM includes several bit lines (Bit Line, BL) and several polysilicon word lines (Word Line, WL) straddling the bit lines. The area below the word line and between two adjacent bit lines is the channel area of ​​the memory cell. For some mask ROMs, the programming method is to store data "0" or "1" by whether ions are implanted in the channel or not. The process of implanting ions in specific channel regions is also called code implantation process. [0003] Generally, the code implantation process of the mask read-only memory is to firstly use a photomask to pattern the photoresist layer formed on the substrate, so as to expose the desired code implantation region. Then, an ion implantation process is perfor...

Claims

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Application Information

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IPC IPC(8): H01L21/8246H01L27/112
Inventor 张庆裕
Owner MACRONIX INT CO LTD
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