Tech. for etching capable of controlling grid structural length

A technology of structure length and gate control, applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve the problems of smaller key dimensions, secondary initial leakage of MOS transistors, and achieve the effect of maintaining integrity

Inactive Publication Date: 2006-06-14
GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, when the thickness of the patterned photoresist is not enough to leave enough on the anti-reflection barrier layer before the gate etching is completed, the CD of the gate may be reduced, resulting in Occurrence of Sub-threshold Leakage of MOS transistors

Method used

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  • Tech. for etching capable of controlling grid structural length
  • Tech. for etching capable of controlling grid structural length
  • Tech. for etching capable of controlling grid structural length

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0023] Figure 1 to Figure 4 It is a cross-sectional view of each step of making the gate structure of the present invention; Figure 5 It is a schematic flow chart of the etching process that can control the length of the gate structure in the present invention. In order to describe this preferred embodiment in more detail, please refer to figure 1 and Figure 5 .

[0024] First, proceed to step S10, providing such as figure 1 A silicon substrate 10 is shown, and a gate oxide layer 20 , a polysilicon layer 30 , a hard mask layer 40 and a patterned photoresist 50 are sequentially deposited on the silicon substrate 10 by using chemical vapor deposition technology. The hard mask layer 40 is composed of a TEOS layer 402 and a dielectric layer 404. The TEOS layer 402 is located under the dielectric layer 404. The entire hard mask layer 40 is set because the hard mask layer 40 is patterned The photoresist 50 can also provide a better etching selectivity ratio. When the polysi...

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PUM

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Abstract

The invention relates to an etching process able to control the length of a grid structure, using hard mask to raise the selection ratio of etching polycrystalline silicon layer, and adopting three-stage etching (first primary etching / second primary etching / over etching) in the polycrystalline silicon layer etching process; the first primary etching gas contains carbon tetrafluoride to reinforce the whole patternized hard mask and high molecular film deposit on the side walls of the polycrystalline silicon layer to convert the high molecular film deposit into high molecular film combination; the high molecular film combination can effectively resist the side corrosion of halides to the polycrystalline silicon layer to make the horizontal width of the polycrystalline silicon layer unable to be reduced, and the patternized hard mask can better resist the corrosion of the etching gas to hold the pattern, thus solving the problem of generating initial creepage.

Description

technical field [0001] The invention relates to an etching process capable of controlling the length of a gate structure, in particular to a process for etching a polysilicon layer by using a patterned hard mask layer as a mask. Background technique [0002] Dry etching is basically a process of selectively removing the thin film layer deposited on the chip by using the photoresist produced by photolithography as a mask. The most important condition to measure the success of this project is to be able to completely transfer the pattern size of the photoresist to the etched film 100% without error, especially the etching of the gate, which is even more important, because MOS The initial voltage and saturated drain current of the transistor depend on the length of the gate channel and the width of the gate photoresist. [0003] The usual technology is to perform a typical breakthrough step (open step), main etching step (main etch) on a structure (patterned photoresist / anti-r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/28H01L21/3065H01L21/311H01L21/3213
Inventor 张双燻李化杨王晓武
Owner GRACE SEMICON MFG CORP
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