Surface mount package

Abstract

Space-efficient packaging of microelectronic devices permits greater functionality per unit PC board surface area. In certain embodiments, packages having leads of a reverse gull wing shape reduce peripheral footprint area occupied by the leads, thereby permitting maximum space in the package footprint to be allocated to the package body and to the enclosed die. Embodiments of packages in accordance with the present invention may also reduce the package vertical profile by featuring recesses for receiving lead feet ends, thereby reducing clearance between the package bottom and the PC board. Providing a linear lead foot underlying the package and slightly inclined relative to the PC board further reduces vertical package profile by eliminating additional clearance associated with radiuses of curvature of J-shaped leads.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] The instant non-provisional patent application claims priority from U.S. provisional patent application No. 60 / 291,212, filed May 15, 2001 and entitled “Improved Surface Mount Package”. This provisional patent application is hereby incorporated by reference.BACKGROUND OF THE INVENTION [0002] The present invention relates generally to electronic devices. More particularly, the invention provides an improved package, packaging system and method for packaging of electronic devices. Merely by way of example, the present invention can be used for producing “small footprint sized packages” for integrated circuit devices and discrete devices often used for a variety of digital, analog, small signal discrete, and power applications, such as electronically controlled switches for power on / off control of system and sub-system components, and switching components in DC / DC conversion, especially in mobile and battery powered applications such as cel...

AI Technical Summary

Benefits of technology

[0053] Another embodiment of the present invention includes a semiconductor package with J-shaped or reverse-gull-wing shaped leads containing a lead frame having two separated die pads such that all the pins (for each die pad) on one side of the package are directly connected to the die pad so that heat may easily flow from each die pad into the PC board, where in a preferred embodiment the lead frame is composed of copper or another metal with high electrical and thermal conductivity. Specific examples of this invention include but are not limited to an eight pin package where two pins on the same side of the package are tied to each die pad, an twelve pin package where three pins on the same side of the package are tied to each die pad, and a fourteen pin package where four pins on the same side of the package are directly connected to one die pad, while three pins are tied directly to the other die pad. In a preferred embodiment of this invention the die pad size can be expanded closer to the inside edge of the plastic body (i.e. to a smaller dimension minimum enclosure of the die pad by the plastic body) on the side where the pins are tied to the die pad than the minimum enclosure of the die pad by the plastic body on the opposite side of the package where the pins are not connected to the die pad, thereby allowing a larger die pad facilitating the maximum possible die size to fit within the package.

[0054] Anothe...

Problems solved by technology

Such packages are often very small as compared to more conventional integrated circuit device packages (e.g., BGAs, PLCC, QFP, PGA) for conventional large DSPs (digital signal processors), ASICs (application specific integrated circuits), memory devices (e.g., Flash, DRAM, ROM) for computers, microprocessors (e.g., Intel™ Pentium), and the like, which often use very high pin counts and extremely large die sizes.

Although there has been much development with package designs for conventional devices, to date there has been little focus on improving the design of packages for the smaller, low pin count and low integration devices, especially for power applications.

Many conventional small footprint packages still lack efficiency and performance.

For example, conventional packages have not been configured to provide enhanced performance per unit area of PC board occupied.

This poor area efficiency limits the functionality or performance of the semiconductor component in its application, especially when the available board space is determined by the maximum allowable size and three-dimensional form-factor of the end product, such as a cell phone.

In this context, poor performance may constitute a lack of desirable features in the semiconductor (features not possible because of a limited amount of available silicon real estate), or as a higher resistance device, transistor, power MOSFET or other switching element leading to increased power losses, self heating, and further increases in resistance as a result of self heating.

These increased power losses can be viewed as both a potential thermal problem, and as a loss in efficiency and battery life.

Furthermore, such small, low-pin count packages typically lack sufficient ability to remove heat from the semiconductor die and to conduct that heat out of the package into the PC board and into the ambient.

The high thermal resistance characteristic of a package's inability to remove heat limits the utility of these conventional type small packages in applications (and in products) where the semiconductor die is forced to dissipate substantial power, even if but for a few seconds.

In high power dissipation conditions, unless the power dissipation is limited, the semiconductor die may malfunction, or be damaged, and may also damage its own package and even other compon...

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