MIM capacitor integrated into the damascene structure and method of making thereof

Abstract

This invention provides for the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. The method includes forming a damascene interconnect structure and a MIM capacitor damascene structure wherein a diffusion barrier material forms the capacitor electrodes. The method includes forming a MIM capacitor damascene structure through an interlevel dielectric layer and terminating on a diffusion barrier material instead of a conventional dielectric etch stop layer. In alternative embodiments, the integrated damascene MIM capacitor makes up part of semiconductor device such as DRAM memory, CMOS, or a high frequency device.

Description

TECHNICAL FIELD [0001] This invention relates generally to semiconductor device fabrication and more particularly to the integration of metal-insulator-metal (MIM) capacitors with the damascene interconnect structure and process. BACKGROUND [0002] Capacitors are critical components of analog integrated circuit devices and memory devices. They are also used in many mixed signal or high frequency applications requiring both high performance and high speed. Low series resistance, low loss, high Q and low (RC) time constants are required in these high frequency applications for high performance. Metal-insulator-metal (MIM) capacitors are commonly used, such as in high performance applications. [0003] MIM capacitors typically include metal electrodes separated by a dielectric. The MIM structure and materials frequently and advantageously allow integration of its fabrication with the damascene interconnect process. In conventional methods, the electrodes are made from Al, Cu, or alloys th...

AI Technical Summary

Benefits of technology

[0007] These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention that provide a method and structure for the creation of a metal-insulator-metal (MIM) capacitor. By using a damascene barrier liner for capacitor plates and an etch stop layer as a capacitor dielectric, fabrication costs are reduced without sacrificing capacitor density or performance.

Problems solved by technology

Conventional MIM capacitors have a relatively small parasitic resistance, however, they also have a number of disadvantages.

Even with an ultra thin gate oxide, high capacitance requires a large silicon area, thereby increasing die size as well as chip and assembly cost.

Ultra thin oxides also lead to unacceptably high leakage currents in integrated circuits (e.g. 100 mA for 0.1 mm2 of 12 Å gate oxide).

These factors cause problems with power and thermal management, they shorten battery life for mobile applications, and they increase overall cost.

Since the cross-sectional area of the capacitor plug is small and the difference in height between damascene and capacitor plugs may be great, etching is very difficult to control.

If the capacitor metal electrode layers and its dielectric layer are formed on an entire layer during fabrication, production costs are very high.

When etching to form the electrodes and dielectric layer, it is very easy to cause damage on the edge portion of the metal capacitor.

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