Integrated parallel plate capacitors

Abstract

A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Description

TECHNICAL FIELD [0001] The field of the invention is that of forming a plate capacitor having a set of horizontal conductive plates separated by a dielectric (MIM-CAP). BACKGROUND OF THE INVENTION [0002] High performance (high Q-value) metal-insulator-metal capacitor (MIM cap) is one of the essential passive devices in RF / Analog circuitry. In order to achieve high-Q value, low resistance metal plates are typically used. In prior work, the bottom plate of a metal-insulator-metal (MIM) capacitor is typically made of back end of the line (BEOL) aluminum metal wire on the xth level of the back end (zero-cost). An additional photolithography mask is used for MIM cap top plate formation. This additional top plate mask leads to extra wafer processing cost of about $25 / wafer. In the advanced CMOS technologies with Cu BEOL, up to three masks are employed to create high-Q MIM capacitors. [0003] In an effort to reduce cost, vertical parallel plate capacitors (VPP) have been recently developed / ...

AI Technical Summary

Benefits of technology

The present invention is a method of creating a high-performance MIM capacitor using wide copper planes and existing inter-level dielectric layers. The Mx electrodes are tied together to create a parallel plate capacitor, which results in low resistance and high capacitance. The capacitance density increases as the inter-level dielectric films become thinner and more metal levels are employed for advanced technologies. The use of through-vias further enhances capacitance density and reduces additional wiring area needed for MIM cap plate connection. The Ansoft Q3D simulation indicates that capacitance density improvement of greater than 30% is possible compared with through-via practice.

Problems solved by technology

This additional top plate mask leads to extra wafer processing cost of about $25 / wafer.

However, the performance of a VPP capacitor is limited because of the high resistance associated with metal fingers / vias, which is particularly troublesome for high frequency application.

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