Dielectric layers and methods of forming the same

Abstract

High dielectric constant (high-k) materials are formed directly over oxidation-susceptible conductors such as silicon. A discontinuous layer is formed, with gaps between grains of the high-k material. Exposed conductor underneath the grain boundaries is oxidized or nitridized to form, e.g., silicon dioxide or silicon nitride, when exposed to oxygen or nitrogen source gases at elevated temperatures. This dielectric growth is preferential underneath the grain boundaries such that any oxidation or nitridation at the interface between the high-k material grains and covered conductor is not as extensive. The overall dielectric constant of the composite film is high, while leakage current paths between grains is reduced. Ultrathin high-k materials with low leakage current are thereby enabled.

Description

REFERENCE TO RELATED APPLICATION [0001] The present application is a divisional of U.S. application Ser. No. 10 / 379,516, filed Mar. 4, 2003 and claims the priority benefit under 35 U.S.C. §119(e) to U.S. provisional application No. 60 / 362,249, filed Mar. 5, 2002.FIELD OF THE INVENTION [0002] The present invention relates generally to the manufacturing of integrated circuits, and more particularly to the preparation of high-k dielectric layers in integrated circuits. BACKGROUND OF THE INVENTION [0003] Process control is very important in the fabrication of ultra-large scale integrated circuits. Through a series of deposition, doping, photolithography and etch steps, the starting substrate and subsequent layers are converted into integrated circuits, with a single substrate producing from tens to thousands or even millions of integrated devices, depending on the size of the wafer and the complexity of the circuits. [0004] One area in which process control is particularly critical is t...

AI Technical Summary

Problems solved by technology

As the chip area or “footprint” available per memory cell shrinks with each progressive generation of integrated circuits, the required capacitance per unit of footprint has increased.

Often, these structures require extremely complex fabrication steps, increasing the cost of processing significantly.

Such high defect densities lead to leakage currents through the dielectric and rapid device breakdown unacceptable for circuit designs with less than 0.25 μm gate spacing, i.e., sub-quarter-micron technology.

Moreover, even if the integrity of the silicon oxide is perfectly maintained, quantum-mechanical effects set fundamental limits on the scaling of silicon oxide.

However, silicon nitride has been found to exhibit a higher density of defects, such as interface trapping states, as compared to oxides.

The benefits of gate dielectrics made from silicon nitride are limited, however, because of the marginal increase in dielectric constant afforded by silicon nitride, particularly when used in conjunction with silicon oxide.

Several factors have limited the integration of such materials into current process flows, including the relative instability of high-k materials, a tendency to exhibit high defect densities, leakage currents, and the difficulty of avoiding oxidation of surrounding materials during high-k dielectric deposition and annealing.

Relatively complex process flows, however, are required to achieve such structures, and the overall dielectric constant of multiple-layer dielectric structures dilutes the effect of the high-k materials.

Images