Method of forming nanoscale three-dimensional patterns in a porous material
a three-dimensional pattern and porous material technology, applied in the field of semiconductor fabrication, can solve the problems of large-area fabrication methods for producing nano-scale (100 nm) patterned porous silicon, inability to achieve spatial resolution of these techniques, and inability to achieve large-scale etching damage, etc., to achieve the effect of facilitating wafer level packaging integration
Active Publication Date: 2011-10-27
THE BOARD OF TRUSTEES OF THE UNIV OF ILLINOIS
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[0004]The inventors have developed a method of forming a nanoscale three-dimensional pattern in a porous material that may provide advantages over existing technologies. The method
Problems solved by technology
The spatial resolution of these techniques may be limited by lithography tools or by the fragility and reactivity of porous silicon during formation or etching.
As a result, a large-area fabrication
Method used
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[0045]Various nanoscale patterns, including dot, mesh, lines, grids, boomerang contour arrays in the range of from about 10 nm to about 100 nm in dimension, were written on PMMA on p− type (100) Si substrates (7 Ωcm) using electron beam lithography at 50 kV. Platinum (Pt) and titanium (Ti) metals were evaporated and followed with standard lift-off. Metal patterned substrates were then etched in a H2O2 metal-HF (HOME-HF) etchant for 15˜60 seconds. Morphology resulted from etching was examined with scanning electron microscopy (SEM) and atomic force microscopy (AFM). Optical properties of the etched samples were also characterized, as described in Chun et al., Applied Physics Letters 92, 191113 (2008) 1-3, which is hereby incorporated by reference in its entirety.
[0046]Shown in FIG. 3A is a SEM image of an array of Ti / Pt dots of 15 nm in height (5 nm Ti followed by 10 nm Pt), 15 nm in diameter and 100 nm in pitch patterned on a p− type silicon substrate. FIG. 3B shows the pattern afte...
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A method of forming a nanoscale three-dimensional pattern in a porous semiconductor includes providing a film comprising a semiconductor material and defining a nanoscale metal pattern on the film, where the metal pattern has at least one lateral dimension of about 100 nm or less in size. Semiconductor material is removed from below the nanoscale metal pattern to create trenches in the film having a depth-to-width aspect ratio of at least about 10:1, while pores are formed in remaining portions of the film adjacent to the trenches. A three-dimensional pattern having at least one nanoscale dimension is thus formed in a porous semiconductor, which may be porous silicon. The method can be extended to form self-integrated porous low-k dielectric insulators with copper interconnects, and may also facilitate wafer level chip scale packaging integration.
Description
TECHNICAL FIELD[0001]The present disclosure is directed generally to semiconductor fabrication and more particularly to a method of forming nanoscale three-dimensional patterns in porous semiconducting materials.BACKGROUND[0002]Porous silicon is a nanostructured material that may be composed of interconnected crystallites and pores having a dimension of 1-100 nm. Promising approaches for micron- and submicron-scale pattern formation in porous silicon have been reported using either lithography methods, which selectively mask the porous silicon removal or generation, or maskless localized treatments of silicon surfaces, which block or enhance porous silicon formation or dissolution. Among the specific techniques used include ion irradiation or implantation, electron beam lithography and irradiation, localized far-field or near-field illumination, dry-removal soft lithography, and lithography with a multilayer electrochemical resistant mask. The spatial resolution of these techniques ...
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CPCH01L21/30604H01L21/3085H01L2924/0002H01L2924/10329H01L2924/01078H01L21/76816H01L21/7682H01L23/291H01L23/3171H01L24/03H01L24/05H01L24/81H01L25/0657H01L25/18H01L2221/1047H01L2224/0346H01L2224/0401H01L2224/05022H01L2224/05073H01L2224/05562H01L2224/05567H01L2224/05573H01L2224/131H01L2224/16147H01L2224/81191H01L2224/81801H01L2225/06513H01L2225/06568H01L2924/01013H01L2924/01029H01L2924/01032H01L2924/01073H01L2924/01079H01L2924/014H01L2924/10253H01L2924/14H01L2924/01006H01L2924/01019H01L2924/01023H01L2924/01033H01L2924/01072H01L2224/05552H01L2224/03334
Inventor LI, XIULINGRUZIC, DAVID N.CHUN, IK SUCHOW, EDMOND K.C.FLAUTA, RANDOLPH E.
Owner THE BOARD OF TRUSTEES OF THE UNIV OF ILLINOIS
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