Stackable semiconductor assembly with bump/base/flange heat spreader and electromagnetic shielding

Abstract

A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a terminal, a plated through-hole and build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry provides signal routing for the semiconductor device. The plated through-hole provides signal routing between the build-up circuitry and the terminal. The heat spreader provides heat dissipation for the semiconductor device.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims the benefit of filing date of U.S. Provisional Application Ser. No. 61 / 415,862, entitled “SEMICONDUCTOR CHIP ASSEMBLY WITH BUMP / BASE HEAT SPREADER, CAVITY IN BUMP AND EXTENDED CONDUCTIVE TRACE” filed Nov. 22, 2010 under 35 USC §119(e)(1).BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to semiconductor assembly, and more particularly to a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole and build-up circuitry.[0004]2. Description of Related Art[0005]In the field of electronic systems, there is a continuous need to improve performance and reduce size and weight. Many approaches have been proposed to meet these requirements and strike a balance between performance optimization, time-to-market expedition and cost reduction through the use of different architectures, materials, equipment, process nodes...

AI Technical Summary

Benefits of technology

[0032]The present invention has numerous advantages. The heat spreader can provide excellent heat spreading and heat dissipation without heat flow through the adhesive or the substrate. As a result, the adhesive and the substrate can be a low cost dielectric and not prone to delamination. The bump and the flange can be integral with one another, thereby providing excellent electromagnetic shielding and a moisture barrier for better electrical performance and environmental reliability. The mechanically-formed cavity in the bump can provide a well-defined space for semiconductor device placement. As a result, the likely shifting and cracking of the embedded chip during lamination can be avoided, thereby enhancing manufacturing yield and reducing cost. The base can include a selected portion of the metal layer associated with the substrate, thereby enhancing thermal performance. The metallic nature of base can also provide mechanical support for the substrate, thereby preventing warping. The adhesive can be sandwiched between the bump and the substrate, between the base and the substrate and between the flange and the substrate, thereby providing a robust mechanical bond between the heat spreader and the substrate. The build-up circuitry can provide electrical connections to the semiconductor device with plated metal without wire bonds or solder joints, thereby increasing reliability. The build-up circuitry can also provide signal routing with simple circuitry patterns or flexible multi-layer signal routing with complex circuitry patterns. The plated through-hole can provide vertical signal routing between the build-up circuitry and the terminal, thereby providing the assembly with stacking capability.

Problems solved by technology

Furthermore, as there are significant obstacles to further reduce chip feature sizes below the nanometer range due to significant expense for material, equipment and process developments, attention has therefore shifted to packaging technologies to timely fulfill the relentless demands for a smarter and smaller device.

Despite numerous three-dimensional packaging architectures reported in the literature, many performance-related deficiencies remain.

For instance, multiple devices stacked in a limited space often encounter undesirable inter-device noise such as electromagnetic interference (EMI).

The signal integrity of the stacked devices can be adversely affected when they perform high frequency transmitting or receiving of signals.

Furthermore, as semiconductor devices are susceptible to performance degradation and immediate failure at high operating temperatures, collective heat generated from the chips enclosed in a thermally insulating material such as dielectrics can cause catastrophic damage to the assembly.

However, as most plastic material has low thermal conductivity, this plastic assembly suffers poor thermal performance and offers no electromagnetic shielding protection for the embedded chips.

U.S. Pat. No. 5,432,677 to Mowatt et. al., U.S. Pat. No. 5,565,706 to Miura et al., U.S. Pat. No. 6,680,529 to Chen et al. and U.S. Pat. No. 7,842,887 to Sakamoto et al. disclose various embedded modules to address manufacturing yield and reliability concerns, None of these approaches offers a proper thermal dissipation solution or effective electromagnetic protection for the embedded chi

Since the cavity in the substrate is formed by laser or plasma etching of the substrate, the major drawbacks include low throughput and high cost in forming the cavity in addition to the limited heat dissipation capability of the bottom metal layer in the structure.

Inconsistent cavity depth control of the recess in the metal plate can result in low throughput and low yield in volume production.

Furthermore, as the thick metal plate would electrically block the vertical connection to the bottom surface, resin filled holes need to be created before metallized plated through-holes can be built in the metal block.

The cumbersome process makes the manufacturing yield excessive low and costly.

Much like many other cavity type approaches, this assembly suffers poor manufacturing throughput and low yield due to slow cavity formation in the resin.

Furthermore, since the metal-plated cavity is embedded in the resin, it does not improve the package's thermal performance.

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