Semiconductor process

Abstract

A semiconductor structure includes at least a fin-shaped structure, a gate, a source / drain region, an interdielectric layer and an epitaxial structure. At least a fin-shaped structure is located on a bottom substrate. The gate covers the fin-shaped structure. The source / drain region is located in the fin-shaped structure next to the gate. The interdielectric layer covers the gate and the fin-shaped structure, wherein the interdielectric layer has a plurality of contact holes, respectively exposing at least a part of the source / drain region. The epitaxial structure is located in each of the contact holes, directly contacts and is only located on the source / drain region. Additionally, a semiconductor process formed said semiconductor structure is also provided.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a divisional application of and claims the benefit of U.S. patent application Ser. No. 13 / 351,231, filed Jan. 17, 2012.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates generally to a semiconductor structure and process thereof, and more specifically, to a semiconductor structure and process thereof, which directly forms an epitaxial structure in a contact hole.[0004]2. Description of the Prior Art[0005]Epitaxy technology is often used to form semiconductor components. The functions of the epitaxy technology are that not only can a whole single-crystalline silicon layer be formed but also problems caused in semiconductor processes can be solved. In addition, the epitaxy technology may also be used to form semiconductor components having particular functions. For instance, as a silicide process is performed, a metal layer will cover a source / drain region, so that metals in the...

AI Technical Summary

Benefits of technology

This approach prevents short circuits and allows for the scaling down of semiconductor components by controlling the size and shape of the epitaxial structure, enhancing the layout and performance of devices like SRAM.

Problems solved by technology

When silicon in the source / drain region over-reacts with the metal layer or the source / drain region is too shallow, however, the source / drain region will deplete after reacting, leading to a break down in the p-n junction.

As the semiconductor processes advance to the very deep sub-micron era such as 65-nm node or beyond, how to increase the driving current for MOS transistors has become a critical issue.

Even worse, this causes each adjacent fin-shaped structure to be merged together, giving rise to a short circuit of the semiconductor component.

A way of preventing this short circuit is providing enough space between each fin-shaped structure; however, this would restrict the size of the semiconductor component and prevent the desired scaling down.

The problem becomes particularly significant in a static random access memory (SRAM) having dense distribution of fin-shaped structures.

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