Through silicon via packaging structures and fabrication method

Abstract

A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]This application claims the priority of Chinese patent application No. 201210299744.9, filed on Aug. 21, 2012, the entirety of which is incorporated herein by reference.FIELD OF THE INVENTION[0002]The present invention generally relates to the field of semiconductor manufacturing technology, and more particularly, relates to through silicon via packaging structures and techniques for fabricating high-performance integrated chips.BACKGROUND[0003]With the development of the semiconductor technology, the critical size of semiconductor devices has become very small, it is becoming more difficult to include more semiconductor devices in a two-dimensional packaging structure, therefore a three-dimensional packaging becomes an effective method for improving the integration density of chips. Current three dimensional packaging techniques include die stacking and package stacking based on gold wire bonding and three-dimensional stacking based on ...

AI Technical Summary

Benefits of technology

The patent text describes a method for making silicon via that reduces production cost and prevents damage to the sidewall of the via while maintaining good electrical properties. By controlling the thickness of the silicon substrate formed by epitaxial growth or chemical vapor deposition (CVD), the depth of the silicon via can be controlled. This allows for easier control of the overall thickness of the final silicon substrate and the depth of the silicon via.

Problems solved by technology

However, existing methods for forming a TSV structure may often need a chemical mechanical polishing (CMP) process to back grind the silicon substrate.

The CMP process may generate stress effect on the silicon substrate and, thus, the thickness of the silicon substrate after the back grinding process cannot be very small.

Therefore, the depth of the TSV may also be at least 200 μm, the process for forming the TSV structure become more complex, and the production cost is increased.

Images