Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for forming nanowire wide polycrystalline silicon gate etching mask images

A technology of polysilicon gate and etching mask, which is applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve problems such as inaccessibility, and achieve the effect of easy realization and reliable method

Inactive Publication Date: 2007-10-10
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, even the most promising electron beam exposure can only reach the line width level of about 100 nanometers, and the line width of sub-50 nanometers cannot be reached.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for forming nanowire wide polycrystalline silicon gate etching mask images
  • Method for forming nanowire wide polycrystalline silicon gate etching mask images
  • Method for forming nanowire wide polycrystalline silicon gate etching mask images

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0030] Step 1: grow a 200nm polysilicon film on an ultra-thin gate dielectric film with an equivalent oxide thickness (EOT) of 1.4nm, and then deposit 75nm orthosilicate at 720°C to thermally decompose SiO 2 membrane.

[0031] Step 2: Use SAL 601 negative glue, electron beam direct writing lithography to form 100-110 nanometer glue pattern. Figure 1 shows the schematic diagram of the structure after exposure.

[0032] Step 3: Carry out the ashing of the glue, the radio frequency power is 60 watts, and the reaction gas is O 2 40sccm, diluting gas He 60sccm, working pressure 450mτ, electrode distance 1.5cm, electrode temperature 35°C. The etching rate is about 75-80 nm / min, and the glue line width is controlled to be 50-55 nm. Figure 2 shows the SEM photo of the rubber grid pattern after the ashing process, and the line width after ashing is 54.9 nm.

[0033] Step 4: Fluorination and baking, RF power 40 watts, CF 4 100sccm, He 60sccm, working pressure 500mτ, fluorination ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

This invention relates to nanometer wide multi-silicon grating etching mask film pattern forming method, which comprises the following steps: a, depositing multi-silicon on the super thin grating medium and then depositing thin film of TEOS Sao2; b, etching the grating pattern; c, processing the glue gray step; d, fluoride and drying; e, etching the reaction ion of TEOS Sao2; f, removing the glue and clearing; g, processing the humid chemical erosion of TEOS Sao2 to achieve the needs. The invention can process the multi-silicon grating mask film pattern of fifteen to fifty nanometers.

Description

technical field [0001] The invention belongs to a process method of an ultra-deep submicron semiconductor device, in particular to a method for forming a polysilicon gate etching mask pattern with a line width of 15-50 nanometers. Background technique [0002] The reduction in transistor features can lead to increases in integrated circuit density and performance as well as a reduction in the cost amortized in unit functions. Therefore, since the birth of the integrated circuit, the competition in the semiconductor industry has always focused on the miniaturization of the processing size. The feature size (physical gate length) for mass production in 2010 was 18 nanometers. The reduction of the device size to sub-50nm is close to the limit of Scaling down, and it will face severe technical challenges, mainly in the difficulties caused by certain parameters of the device, such as threshold voltage and power supply voltage. channel effect, excessive off-state leakage current...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/027H01L21/336H01L21/8234
Inventor 徐秋霞钱鹤刘明赵玉印
Owner SEMICON MFG INT (SHANGHAI) CORP