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Thin film transistor of multi-grid structure and manufacturing method thereof

A technology of thin-film transistors and manufacturing methods, which is applied in the field of thin-film transistor array substrates, and can solve problems such as LDD region position offset, difficult control, and electrical asymmetry of transistors

Inactive Publication Date: 2008-06-25
TPO DISPLAY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, limited by the photo misalignment of the exposure technology, it is not easy to control the four N - Doped region 14a 1 、14a 2 、14a 3 、14a 4 The length symmetry of the LDD region will occur, and the position shift phenomenon of the LDD region will occur, which will lead to the problems of electrical asymmetry, complicated manufacturing process and low yield of the transistor.

Method used

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  • Thin film transistor of multi-grid structure and manufacturing method thereof
  • Thin film transistor of multi-grid structure and manufacturing method thereof
  • Thin film transistor of multi-grid structure and manufacturing method thereof

Examples

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no. 1 example

[0053] see Figure 2A to Figure 2E , which shows a schematic cross-sectional view of a method for fabricating a polysilicon TFT with a double-gate structure according to the first embodiment of the present invention.

[0054] First, if Figure 2A As shown, a substrate 30 is provided, and a buffer layer 32 and an effective layer 34 are sequentially fabricated on the substrate 30 . The substrate 30 is preferably a transparent insulating substrate, such as a glass substrate. The buffer layer 32 is preferably a dielectric material layer, such as a silicon oxide layer, and its purpose is to help the effective layer 34 to be formed on the substrate 30 . The effective layer 34 is preferably a semiconductor silicon layer, such as a polysilicon layer. In order to adjust the threshold voltage of the transistor, a boron or phosphorus ion implantation (B + or P + ion implantation) process.

[0055] Then, if Figure 2B As shown, an insulating layer 36 and a conductive layer 38 are s...

no. 2 example

[0070] see image 3 , which shows a schematic cross-sectional view of a polysilicon TFT with a double gate structure according to the second embodiment of the present invention. The structural features of the thin film transistor in the second embodiment are substantially the same as those described in the first embodiment, and the similarities will not be described again. The difference is that the first gate insulating layer 40 additionally includes an extension region 40c, which is the first shielding region 40b 1 and extend to cover the seventh region 347 of the effective layer 34 . It is characterized in that the thickness of the extension region 40c is much smaller than that of the first shielding region 40b 1 The thickness will not affect the fabrication of the LDD region and the source / drain region. Similarly, the second gate insulating layer 42 additionally includes an extension region 42c, which is a second shielding region 42b 2 and extend to cover the eighth re...

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Abstract

This invention is a multi-grid film transistor and its manufacturing method. It takes advantage of the covering area formed by the grid insulation exposing to the two sides of the grid layer as the cover of the ion arrangement process, and meanwhile complete the manufacturing of LDD area and source / drain areas. Set LDD area at the two sides of every grid layer, and make the multi-crystal silicon transistor have extremely low leakage current and avoid the problem of yellow light adjust and reach to the length symmetry of LDD area.

Description

technical field [0001] The invention relates to a thin film transistor array substrate technology of a liquid crystal display, in particular to a thin film transistor with a multi-gate structure and a manufacturing method thereof. Background technique [0002] A thin film transistor (TFT) of a liquid crystal display (hereinafter referred to as LCD) is used as a switch element of a pixel, and generally can be divided into two types: amorphous silicon TFT and polysilicon TFT. Because polysilicon TFTs have higher carrier mobility, better integration of driving circuits, and smaller leakage currents, polysilicon TFTs are often used in circuits with high operating speeds. However, the current in the on (on) and off (off) states of the polysilicon TFT is very large, and a large electric field will be generated in the depletion region adjacent to the drain region, so the energy gap generated by material defects and tunneling effect is extremely large. It is easy to make the electr...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L21/336G02F1/136
Inventor 张世昌曾章和邓德华蔡耀铭
Owner TPO DISPLAY
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