Non-volatile memory device and design method thereof

Abstract

The present invention discloses a nonvolatile storage device and its design method, and includes: metal layer, contact hole, barrier layer and transistor. The transistor includes polysilicon layer; the metal layer and the contact hole form a controlling gate; being objected by the barrier layer, the polysilicon layer does not directly join the contact hole to form floating gate; the metal layer, contact hole, barrier layer and polysilicon layer are orderly joined to form capacity structure. The present invention obviously improves capacity density of the coupling capacitor of the controlling gate and the floating gate, reduces area of the storage element, and is good to integrate connections of system metal wires.

Description

technical field [0001] The present invention mainly relates to a semiconductor storage device, in particular to a non-volatile storage device and a design method thereof. Background technique [0002] The manufacture of a System On Chip (SOC, System On Chip) is mainly based on a logic process, and designers often need to integrate a large number of non-volatile storage units when designing an SOC. The manufacturing process of the existing non-volatile memory needs to adopt the special process besides the logic process, the logic process is the mainstream process generally used by most IC (Integrated Circuits) designers, but the special process is different from the logic process There is a big difference. Since the special process required for the manufacture of non-volatile memory is not commonly used, if this special process is used to develop and manufacture SOC devices, it will cost a lot of cost, and the price of the manufactured SOC devices will be lower than that of ...

AI Technical Summary

Problems solved by technology

Since the special process required for the manufacture of non-volatile memory is not commonly used, if this special process is used to develop and manufacture SOC devices, it will cost a lot of cost, and the price of the manufactured SOC devices will be lower than that of logic chips. Process-manufactured SOC devices are much more expensive

[0003] In addition, although this special process can be used to manufacture the entire SOC for the convenience of manufacturing non-volatile memory, the price paid is that the performance of other logic devices is greatly reduced

Since many IC designers are not as familiar with this special process as they are with traditional logic processes, the method of using this special process to manufacture the entire SOC increases design risk and complexity, and worse, high cost and lag. Technical Support

Among them, the delayed technical support will cause a delay in the entire SOC development time, and the main reason for the delayed technical support is that this special process has not been widely used in the semiconductor manufacturing industry.

[0004] Non-volatile memories based on logic technology mainly include the following schemes: one is composed of P-type metal-oxide semiconductor (PMOS, P type Metal-Oxide Semiconductor) and N-type metal-oxide semiconductor (NMOS, N type Metal-Oxide Semiconductor) for the memory cell structure, in order to prevent the latch-up effect during high-voltage operation, the PMOS and NMOS in this structure must maintain a large interval, which takes up a large area; the second is to use the coupling capacitor of the same layer of metal to control the floating gate Due to the relatively small capacitance density of metal coupling capacitors on the same layer, this structure often needs to occupy a large metal area and multi-layer metal, which is not conducive to the metal wire connection inside the integrated chip.

In addition, the storage of data is achieved by using the soft breakdown and hard breakdown effects to generate a series of different impedances. However, in view of the control difficulty and some unknown effects during the breakdown operation, by using the soft breakdown and hard breakdown The programmable times of non-volatile memory designed with wear-through effect will be very limited

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