Method for manufacturing dent source leakage field effect transistor

Abstract

The invention provides a process for preparing transistors of recessed source-drain field effect, belonging to the field of ultra large scale integrated circuit technique (ULSI). The method introduces epitaxial process and employs the method of sacrificial layers, and two 'L' shaped buried oxide structures are introduced in substrates. By employing the process, processing parameter and physical parameter of devices can be well controlled, such as parameters of reverse doping concentration and depth, junction depth, depth of recessed source-drain, thickness of buried oxide layers and the like.The method is quite strong in controllability and compatible with the existing technique, and is favorable for application in mass production.

Description

technical field [0001] The invention belongs to the field of ultra-large-scale integrated circuit technology (ULSI), in particular to a method for preparing a recessed source-drain field-effect transistor. Background technique [0002] With the development of microelectronics technology, the feature size of devices has entered the deep submicron (<0.1um) range. At this time, the field effect transistors prepared by the traditional CMOS bulk silicon technology are greatly limited in application due to the severe short channel effect and other parasitic effects. SOI (silicon on insulator) devices prepared by using SOI substrate silicon wafers, especially fully depleted SOI devices, can well suppress the short channel effect, obtain small threshold voltage fluctuations and near ideal sub-threshold slopes; at the same time, the Devices fabricated on SiO 2 On the other hand, the parasitic junction capacitance can be reduced, thereby increasing the speed of the device. Howev...

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Problems solved by technology

[0003] Although the above structure has many excellent properties, there are still many difficulties in the actual process realization

The main challenges are: (1) source and drain of single crystal silicon need to be realized to reduce parasitic resistance; (2) source and drain regions need to be fully recessed to reduce parasitic capacitance; (3) how to introduce silicon oxide layer to surround source and drain regions part, and stress cannot be introduced at the same time; (4) The controllability of process realization (such as precise control of junction depth, raised source and drain height, etc.), etc.

At present, the existing preparation methods cannot completely solve these problems

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