Semiconductor device, p-type MOS transistor and manufacturing method thereof

Abstract

The invention relates to a semiconductor device, a p-type MOS transistor and a manufacturing method thereof. The method for manufacturing the semiconductor device comprises the following steps: providing a semiconductor substrate; taking a grid medium layer and a grid electrode as masks, and implanting fluorine ions into a semiconductor substrate in a high-voltage device region; taking the grid medium layer and the grid electrode as the masks, and implanting low doped ions into a semiconductor substrate in the p-type MOS transistor region of the high-voltage device region; performing quick thermal annealing; forming side walls on both sides of the grid medium layer and the grid electrode in the high-voltage device region; and forming a heavy doping source / drain region in the semiconductorsubstrate of the high-voltage device region. The invention also provides the semiconductor device, the p-type MOS transistor and the manufacturing method thereof. The invention is favorable for restricting the influence of the NBTI effect on the MOS transistor by forming a fluorine ion implantation region on a low doping source / drain region in the p-type MOS transistor region of the high-voltage device region, and simultaneously can reduce the hot carrier injection effect.

Description

technical field [0001] The invention relates to the field of semiconductor technology, in particular to a semiconductor device, a p-type MOS transistor and a manufacturing method thereof. Background technique [0002] With the development of technology and the shrinking of device size, the failure of p-type MOS transistors due to the influence of negative temperature bias instability effect (NBTI) is becoming more and more serious. NBTI effect has become a focus problem affecting device reliability. . The NBTI means that the threshold voltage of the p-type MOS transistor drifts under stress at high temperature, so NBTI is an important reliability requirement. With the further development of miniaturization of interconnection, the gate dielectric layer tends to become thinner, so that the NBTI effect needs to be further improved. [0003] At present, although the exact cause of NBTI has not been elucidated, known experience shows that when the concentration of Si-H bonds in...

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Problems solved by technology

[0008] However, in the above technical scheme, due to the use of hydrogen in the oxidation and annealing process, there will always be some Si-H bonds at the silicon-oxygen interface when silicon oxide is formed, which is difficult to completely remove. The key will enhance the NBTI effect and affect the performance of MOS transistors

[0009] Moreover, these Si-H bonds at the interface between the semiconductor substrate and the gate dielectric layer will bring another problem, that is, when a strong electric field exists, it is very easy to be bombarded by hot electrons and break, forming a large number of electron traps, which will seriously affect the semiconductor performance. Device characteristics and reliability, especially in high-voltage devices, that is, input and output devices, due to the strong electric field, these defects are more prone to the hot electron injection effect caused by avalanche impact ionization

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