Method for flexible cantilever bonding of microelectronics system in package

Abstract

The invention discloses a method for flexible cantilever bonding of microelectronics system in package, wherein, a bottom layer chip (2) is bound onto a substrate (1), an upper layer chip (3) is boundto the bottom layer chip (2) through silver coating or alloying technology, the superposed upper layer chip (3) forms a cantilever, an I / O pad (4) of the upper layer chip (3) is connected with pins of the substrate via a micro lead (8) to thereby realize IC packaging interconnection, an interconnection soldered ball is soldered, in the process of bonding, to the chip pad (4) by applying high-frequency ultrasonic energy (5) and bonding pressure (6) which achieves energy transferring through a micro soldered chopper (9), and a flexible polymer (7) is arranged between the bottom layer of the pad(4) and the upper layer chip (3). The invention reduces ultrasonic vibration impact in the process of bonding so that polymorphic energy is steadily responsive in bonding interface, thus effectivelyoffering SiP packaging reliability and bonding strength of the cantilever bonding.

Description

technical field [0001] The invention relates to a flexible cantilever bonding method for microelectronic system-in-package. Background technique [0002] Microelectronic packaging has an important impact on the volume, performance, reliability, quality, and cost of integrated circuit (IC) products. 40% of IC costs are used for packaging, and more than 25% of the failure factors in the IC failure rate come from Packaging affects the general trend of high-performance miniaturization of electronic products. With the development of IC in the direction of system integration, in recent years, system-in-package (SiP) technology has been adopted to solve IC system integration and quickly enter the market. Bare chips with different functions and different processes are connected together to form an IC system through the interconnection of metal wire bonding. [0003] At present, the form of SiP can be said to be ever-changing. As far as the arrangement of chips is concerned, SiP ma...

AI Technical Summary

Problems solved by technology

[0004] Cantilever stacking needs to achieve I / O interconnection bonding on the cantilever. Due to the bonding process of the cantilever, the bottom of the chip at the cantilever end is in an unsupported state. When pressure and ultrasound are applied to the cantilever bonding, the cantilever end is subjected to pressure and ultrasonic vibration. The impact can affect the effective application of cantilever bonding energy and reduce the bonding strength. Experimental tests show that the bonding strength of the cantilever bonding point is 30% lower than the conventional bonding strength. In particular, the impact of pressure and ultrasonic vibration can also cause the chip to be broken and brittle. Chip cracks seriously affect the bonding reliability. How to effectively apply and absorb external field energy on stacked chip cantilever bonding to achieve high-strength, high-reliability bonding; it is necessary to explore new technology to achieve high-strength, high-reliability cantilever Bonding is a key issue that urgently needs to be solved in the development of SiP system integrated packaging

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