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Novel CMOS integrated circuit resisting total dose radiation

A total dose irradiation, integrated circuit technology, applied in the field of electronics, can solve problems such as increasing integrated circuit power consumption, large off-state leakage current, etc., to eliminate parasitic leakage, wide application prospects, and enhance resistance to total dose irradiation Effect

Inactive Publication Date: 2010-03-03
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Before the device supervisor is turned on, the supervisor is in the off state, but at this time the parasitic tube has been turned on, resulting in a large off-state leakage current
This off-state leakage current will greatly increase the power consumption of the integrated circuit, and have a relatively large negative impact on the reliability of the integrated circuit, which has become a total dose radiation reliability problem that needs to be solved urgently at this stage.

Method used

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  • Novel CMOS integrated circuit resisting total dose radiation
  • Novel CMOS integrated circuit resisting total dose radiation
  • Novel CMOS integrated circuit resisting total dose radiation

Examples

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Embodiment Construction

[0019] The present invention will be further described below through a specific preparation example in conjunction with the accompanying drawings.

[0020] This embodiment prepares the CMOS integrated circuit of the novel anti-NMOS device total dose irradiation of the present invention, mainly comprises the following steps:

[0021] 1) Formation of silicon dioxide and silicon nitride. Such as image 3 shown. Thermally oxidize and grow a layer of silicon dioxide with a thickness of about 100 angstroms to 200 angstroms on the bulk silicon substrate 1 as a stress buffer layer 2 between silicon nitride and the silicon substrate, and then use low-pressure chemical vapor deposition (LPCVD) method to deposit a layer of 1000 angstrom to 1500 angstrom silicon nitride as the barrier layer 3 .

[0022] 2) First trench lithography and etching. Such as Figure 4 shown. After defining the shown pattern with the first photolithography plate lithography, the trapezoidal trench 4 is etch...

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Abstract

The invention discloses a novel CMOS integrated circuit resisting total dose radiation, belonging to the technetronic field. The CMOS integrated circuit comprises NMOS devices and PMOS devices; the devices are separated through grooves; grooves among the PMOS are filled with barrier materials I which generate fixed positive charge under total dose radiation; and grooves among the NMOS are filled with barrier materials II which generate fixed negative charge under the total dose radiation. In addition, grooves between NMOS and PMOS are filled with barrier materials I and II, wherein the barriermaterials I are close to PMOS and the barrier materials II are close to NMOS; or NMOS and PMOS are separated by two adjacent grooves, the groove adjacent to PMOS is filled with the barrier materialsI and the groove adjacent to NMOS is filled with the barrier materials II. The invention can be applied to the field related to total dose radiation such as aerospace, military, nuclear power, high energy physics and the like.

Description

technical field [0001] The invention relates to a CMOS integrated circuit, in particular to a novel CMOS integrated circuit capable of resisting total dose radiation, which belongs to the field of electronic technology. Background technique [0002] Integrated circuit technology is being more and more widely used in industries related to total dose radiation, such as aerospace, military, nuclear power and high-energy physics. Moreover, with the continuous improvement of the integration level of integrated circuits, the size of semiconductor devices is decreasing day by day. Shallow trench isolation technology is becoming the mainstream technology for electrical isolation between devices in integrated circuits due to its excellent device isolation performance. However, due to the damage of the silicon dioxide oxide layer in the device by the total dose of irradiated particles, a large amount of fixed positive charges will be generated in the oxide layer of the shallow trench ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/092H01L23/552H01L21/8238H01L21/76
Inventor 刘文黄如
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP
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