Thin film transistor, method for manufacturing thin film transistor, and display device
A technology of thin film transistors and manufacturing methods, applied in the direction of transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of small conduction current, limited space, difficulty in improving the mobility of amorphous silicon TFT, etc., and achieve the suppression of jumping , reduced leakage current, and good on-current characteristics
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
Embodiment approach 1
[0066] figure 1 It is a cross-sectional view schematically showing the structure of the thin film transistor 10 according to the first embodiment of the present invention. Such as figure 1 As shown, the thin film transistor 10 is an inverted staggered TFT having a bottom gate structure, which includes: a gate electrode 12 formed on a glass substrate 11; a gate insulating layer 13 formed on the glass substrate 11 to cover the gate electrode 12 ; the microcrystalline silicon layer 14 as an active layer formed on the gate insulating layer 13; the contact layers 15 (first contact layer) and 16 (second contact layer) formed on the microcrystalline silicon layer 14; source electrode 17 and drain electrode 18 on contact layer 15 and contact layer 16 ; and channel protection layer 19 .
[0067] The microcrystalline silicon layer 14 has an upper surface 14a and a lower surface 14b substantially parallel to the substrate surface (the surface of the glass substrate 11 or the substrat...
Embodiment approach 2
[0114] Next, a thin film transistor 50 according to a second embodiment of the present invention will be described.
[0115] Figure 4 is a cross-sectional view schematically showing the thin film transistor 50 . Such as Figure 4 As shown, the thin film transistor 50 is a staggered TFT with a top gate structure, which includes: a contact layer (first contact layer) 55 and a contact layer (second contact layer) 56 formed on a glass substrate 51; Silicon oxide layers (insulating layers) 61 and 62 on the layers 55 and 56; the microcrystalline silicon layer 54 as an active layer formed on the glass substrate 51 to cover a part of the silicon oxide layers 61 and 62; formed on the microcrystalline silicon layer The gate insulating layer 53 on the gate insulating layer 54; and the gate electrode 52, the source electrode 57 and the drain electrode 58 formed on the gate insulating layer 53.
[0116] The microcrystalline silicon layer 54 has an upper surface 54a and a lower surface ...
PUM
| Property | Measurement | Unit |
|---|---|---|
| thickness | aaaaa | aaaaa |
| thickness | aaaaa | aaaaa |
| thickness | aaaaa | aaaaa |
Abstract
Description
Claims
Application Information
Login to View More 