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Semiconductor chip package structure

A chip packaging structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device components, electric solid-state devices, etc., can solve problems such as difficulties, achieve the effect of reducing parasitic capacitance and weakening the effect of current collapse

Active Publication Date: 2012-10-31
GPOWER SEMICON
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

From a device design point of view, the trade-off between current collapse and fT is a difficult problem

Method used

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  • Semiconductor chip package structure
  • Semiconductor chip package structure
  • Semiconductor chip package structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0025] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0026] figure 1 shows the 80-µs pulsed current-voltage measurements of an AlGaN / GaN high electron mobility transistor with a 2nm SiN passivation layer in air (triangle markers) and vacuum (square markers), and also shows the dc Current and voltage measurement results (circle markers). Among them, the source-drain current (IDS) is used as a function of the source-drain voltage (VDS), and the gate voltage VG corresponding to the DC and 80 microsecond pulse current voltage is measured from the off state (-4V) to 0V, and the step size is 1V (VG= -4, -3, -2, -1, 0V). figure 1 It shows that there is a large DC-RF current collapse effect in the air environment, but there is no current collapse effect in the vacuum environment.

[0027] The same result is also observed for devices passivated by other dielectric layers, for example, devices pas...

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Abstract

The invention provides a semiconductor chip package structure. A semiconductor chip is coated in a coating body in vacuum; the semiconductor chip can be a gallium nitride transistor, a gallium nitride amplifier module or a gallium nitride singlechip microwave integrated circuit; the gallium nitride transistor sequentially comprises a substrate, a semiconductor layer and an isolation layer from bottom to top; the gallium nitride transistor also comprises a source electrode, a drain electrode and a grid electrode; the source electrode and the drain electrode are arranged on the isolation layer and electrically connected to the semiconductor layer; and the grid electrode is arranged on the isolation layer and positioned between the source electrode and the drain electrode. The gallium nitride transistor is packaged in the coating body in vacuum; under the vacuum condition, a passivation layer is not arranged on the surface of a device or a thin passivation layer is arranged on the surface of a device so as to eliminate the current collapse effect of the packaged gallium nitride transistor, and the parasitic capacitance of the packaged gallium nitride transistor can be reduced simultaneously.

Description

technical field [0001] The invention relates to a semiconductor chip packaging structure. Background technique [0002] The dielectric breakdown electric field of the third-generation semiconductor gallium nitride (GaN) is much higher than that of the first-generation semiconductor silicon (Si) or the second-generation semiconductor gallium arsenide (GaAs), up to 3MV / cm, so that its electronic devices can withstand very high voltage. At the same time, gallium nitride can form a heterojunction structure with other gallium-based compound semiconductors (group III nitride semiconductors). Due to the strong spontaneous polarization and piezoelectric polarization effects of III-nitride semiconductors, a two-dimensional electron gas (2DEG) channel with a high electron concentration can be formed near the interface of the heterojunction. This heterojunction structure also effectively reduces the scattering of ionized impurities, so the electron mobility in the channel is greatly ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/02H01L23/16H01L23/28
CPCH01L2924/0002
Inventor 范爱民
Owner GPOWER SEMICON
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