Prescaler with clock-controlled transistor

A prescaler, transistor technology, applied in pulse counters, counting chain pulse counters, electrical components, etc., can solve problems such as poor circuit stability

Active Publication Date: 2010-12-29
杭州中科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this dynamic load structure based on the flip-flop frequency divider has obvious defects. When it changes the load resistance in the sampling phase,

Method used

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  • Prescaler with clock-controlled transistor

Examples

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no. 1 Embodiment

[0074] Such as image 3 Provided is a circuit diagram of the prescaler with clocked transistors in the first embodiment. The prescaler with clocked transistors includes a first flip-flop 30 and a second flip-flop 30 ′. The first flip-flop consists of M 3 and M 4 The sampling differential pair consists of tube 31 and consists of M 5 and M 6 Composed of a latched cross-coupled pair of transistors 32, consisting of MP 1 , MP2 and clock control tube MC 1 consists of load modules 33, and consists of M 1 and M 2 The clock input differential pair consists of transistors 34 . The second flip-flop consists of M 9 and M 10 The sampling differential pair consists of tube 35, and consists of M 11 and M 12 Composed of a latched cross-coupled pair of transistors 36, consisting of MP 3 , MP 4 and clock control tube MC 2 consists of load modules 37, and consists of M 7 and M 8 The clock input differential pair consists of transistors 38 . image 3 , amplifier M 1 ~ M 12 All...

no. 2 Embodiment

[0090] Such as Figure 4 The block diagram of the prescaler with clocked transistors involved in the second implementation example given is a modification of the first implementation example, using a resistive device instead of a MOS tube. The prescaler with clocked transistors includes a first flip-flop 40 and a second flip-flop 40', the first flip-flop 40 consists of M 3 and M 4 The sampling differential pair consists of tube 41, consisting of M 5 and M 6 The latching cross-coupled pair consisting of transistor 42, consists of Z 1 ,Z 2 and clock control tube M C1 consists of load module 43, and consists of M1 and M 2 The clock input differential pair consists of transistor 44 . The second flip-flop 40' consists of M 9 and M 10 The sampling differential pair consists of tube 45, consisting of M 11 and M 12 The latching cross-coupled pair consisting of transistor 46, consists of Z 3 ,Z 4 and clock control tube M C2 consisting of load module 47, and consisting of ...

no. 3 Embodiment

[0092] Such as Figure 5 The block diagram of the prescaler with clocked transistors involved in the third implementation example given is a modification of the first implementation example, using PMOS tubes as amplifier components, and NMOS tubes as load tubes and clock control tubes. The prescaler with clocked transistors includes a first flip-flop 50 and a second flip-flop 50'. The first flip-flop 50 consists of M 3 and M 4 composed of sampled differential pairs 51, consisting of M 5 and M 6 composed of 52 latched cross-coupled pairs, consisting of M N1 ,M N2 and clock control tube M C 1 consisting of a load module 53, and consisting of M 1 and M 2 Composed of the clock input differential amplifier 54'. The second flip-flop 50' consists of M 9 and M 10 consisting of 55 sampled differential pairs, and consisting of M 11 and M 12 composed of 56 latched cross-coupled pairs, consisting of M N3 ,M N4 and clock control tube M C2 Composed of load modules 57, and co...

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Abstract

The invention discloses a prescaler with a clock-controlled transistor, which can provide orthogonal signals. A clock-controlled transistor is added to the structure of a traditional trigger so as to form the prescaler with the clock-controlled transistor, the prescaler with the clock-controlled transistor comprises two triggers, and a clock-controlled transistor controlled by a reverse clock signal is connected with two output ends of each trigger. A dynamic load structure of the trigger with the clock-controlled transistor has low resistance in the sampling stage, thus the charge-discharge time is shortened, the conversion speed is greatly increased, the work frequency is improved, and the shortage of circuit static offset point fluctuation is also overcome; and the dynamic load has high resistance so as to provide enough gain. The one-dimensional high speed low power-consumption prescaler with the clock-controlled transistor has higher work frequency, lower power consumption and wider work range in comparison with the traditional trigger and can keep higher sensitivity.

Description

[0001] Field [0002] The invention belongs to the technical field of integrated circuit design and signal processing, and relates to a high-speed, low-power prescaler, in particular to a prescaler with a clock-controlled transistor. technical background [0003] In recent years, with the rapid development of radio frequency integrated circuit technology, many wireless communication products are used in daily life: GSM mobile phones, 2.4GHz Bluetooth (Bluetooth) products, third-generation mobile communication terminals, mobile phone TV (CMMB) and so on. Products in the field of wireless radio frequency all use frequency synthesizers based on phase-locked loops to generate clock signals and local oscillator signals required by transceivers. The frequency divider is an important part of the phase-locked loop, and its working speed directly determines the application range of the phase-locked loop. The rapid development of wireless communication systems, especially the emergence...

Claims

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Application Information

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IPC IPC(8): H03K23/66
Inventor 于云丰马成炎
Owner 杭州中科微电子有限公司
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